(Ta = 25
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� XRT73LC00AIVTR-F
寤犲晢锛� Exar Corporation
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 8/61闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC LIU STS1/DS3/E3 SGL 44TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1,000
椤炲瀷锛� 绶氳矾鎺ュ彛瑁濈疆锛圠IU锛�
椹�(q奴)鍕�(d貌ng)鍣�/鎺ユ敹鍣ㄦ暩(sh霉)锛� 1/1
瑕�(gu墨)绋嬶細 DS3锛孍3锛孲TS-1
闆绘簮闆诲锛� 3.135 V ~ 3.465 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 44-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 44-TQFP锛�10x10锛�
鍖呰锛� 甯跺嵎 (TR)
XRT73LC00A
13
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
AC ELECTRICAL CHARACTERISTICS
(Ta = 25C, Vdd = 3.3V + 5%, unless otherwise specified)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
Terminal Side Timing Parameters (See Figure 3 & Figure 4)
TCLK Clock Duty Cycle (DS3/STS-1)
30
50
70
%
TCLK Clock Duty Cycle (E3)
30
50
70
%
TCLK Frequency (SONET STS-1)
51.84
MHz
TCLK Frequency (DS3)
44.736
MHz
TCLK Frequency (E3)
34.368
MHz
tRTX
TCLK Clock Rise Time (10% to 90%)
4
ns
tFTX
TCLK Clock Fall Time (90% to 10%)
4
ns
tTSU
TPDATA/TNDATA to TCLK Falling Set up time
3
ns
tTHO
TPDATA/TNDATA to TCLK Falling Hold time
3
ns
tLCVO
RCLK to rising edge of LCV output delay
2.5
ns
tTDY
TTIP/TRING to TCLK Rising Propagation Delay time
0.6
14
ns
RCLK Clock Duty Cycle
45
50
55
%
RCLK Frequency (SONET STS-1)
51.84
MHz
RCLK Frequency (DS3)
44.736
MHz
RCLK Frequency (E3)
34.368
MHz
tCO
RCLK to RPOS/RNEG Delay Time
4
ns
tRRX
RCLK Clock Rise Time (10% to 90%)
2
4
ns
tFRX
RCLK Clock Fall Time (10% to 90%)
1.5
3
ns
Ci
Input Capacitance
10
pF
CL
Load Capacitance
10
pF
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XRT73LC03A 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
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