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參數(shù)資料
| 型號： | XRT73LC00AIVTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 30/61頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU STS1/DS3/E3 SGL 44TQFP |
| 標準包裝： | 1,000 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應商設備封裝： | 44-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
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XRT73LC00A
33
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
3.2
The Receive Equalizer Block
After the XRT73LC00A has received the incoming line signal via the RTIP and RRING input pins, the first block
that this signal passes through is the AGC (Automatic Gain Control) circuit followed by the Receive Equalizer.
As the line signal is transmitted from a given transmitting terminal, the pulse shapes at that location are
basically square. These pulses consist of a combination of “Low” and “High” frequency Fourier components.
As this line signal travels from the transmitting terminal via the coaxial cable to the receiving terminal, it is
subjected to frequency-dependent loss. The higher-frequency components of the signal is subjected to a
greater amount of attenuation than the lower-frequency components. If this line signal travels over reasonably
long cable lengths (e.g., greater than 450 feet), then the shape of the pulses which were originally square is
distorted and inter-symbol interference increases.
The purpose of the Receive Equalizer is to equalize the distortion of the incoming signal due to cable loss. The
Receive Equalizer accomplishes this by subjecting the received line signal to frequency-dependent
amplification which attempts to counter the frequency dependent loss that the line signal has experienced and
to restore the shape of the line signal so that the transmitted data and clock can be recovered reliably.
3.2.1
Guidelines for Setting the Receive Equalizer
This data sheet presents guidelines for setting the Receive Equalizer, for the following conditions.
1. If the overall cable length from the local Receiving Terminal to the remote Transmitting Terminal is NOT
known.
2. If the overall cable length from the local Receiving Terminal to the remote Transmitting Terminal is known.
3.2.1.1
If the Overall Cable Length is NOT Known
This section presents recommendations on what state to set the Receive Equalizer when the overall cable-
length from the local Receiving Terminal to the remote Transmitting Terminal is NOT known. For DS3, STS-1
and E3 applications, enable the Receive Equalizer by setting either the REQDIS input pin “l(fā)ow” or the REQDIS
bit-field to “0”.
The remainder of this section provides an explanation why we recommend enabling the
Receive Equalizer for these applications.
3.2.1.1.1
The Use of the Receive Equalizer in a Typical DS3 or STS-1 Application
Most System Manufacturers of equipment supporting DS3 and STS-1 lines interface their equipment to either
a DSX-3 or STSX-1 Cross-Connect. While installing their equipment the Transmit Line Build-Out circuit is set
to the proper setting that makes the transmit output pulse compliant with the Isolated DSX-3 or STSX-1 Pulse
FIGURE 18. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73LC00A TO THE
LINE (CAPACITIVE-COUPLING)
R1
75
RTIP
RRING
C1
0.01uF
C2
0.01uF
Receive Line Signal
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73LC00IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03A | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03A_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03AES | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73LC03AIV | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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