參數(shù)資料
型號： XRT73LC00AIVTR-F
廠商： Exar Corporation
文件頁數(shù)： 17/61頁
文件大小： 0K
描述： IC LIU STS1/DS3/E3 SGL 44TQFP
標準包裝： 1,000
類型： 線路接口裝置（LIU）
驅動器/接收器數(shù)： 1/1
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 44-LQFP
供應商設備封裝： 44-TQFP（10x10）
包裝： 帶卷 (TR)
XRT73LC00A
21
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
SYSTEM DESCRIPTION
A functional block diagram of the XRT73LC00A E3/DS3/STS-1 Transceiver IC (see Figure 1) shows that the
device contains three distinct sections:
The Transmit Section
The Receive Section
The Microprocessor Serial Interface
THE TRANSMIT SECTION
The Transmit Section accepts TTL/CMOS level signals from the Terminal Equipment in either a Single-Rail or
Dual-Rail format. The Transmit Section then takes this data and does the following:
Encodes the data into the B3ZS format if the DS3 or SONET STS-1 Modes have been selected or into the
HDB3 format if the E3 Mode has been selected.
Converts the CMOS level B3ZS or HDB3 encoded data into pulses with shapes that are compliant with the
various industry standard pulse template requirements.
Drives these pulses onto the line via the TTIP and TRING output pins across a 1:1 Transformer.
NOTE: The Transmit Section drives a "1" (or a Mark) on the line by driving either a positive or negative polarity pulse across
the 1:1 Transformer within a given bit period. The Transmit Section drives a "0" (or a Space) onto the line by driving
no pulse onto the line.
THE RECEIVE SECTION
The Receive Section receives a bipolar signal from the line either via a 1:1 Transformer or a 0.01mF Capacitor.
As the Receive Section receives this line signal it does the following:
Adjusts the signal level through an AGC circuit.
Optionally equalizes this signal for cable loss.
Attempts to quantify a bit-interval within the line signal as either a “1”, “-1” or a “0” by slicing this data. This
sliced data is used by the Clock Recovery PLL to recover the timing element within the line signal.
The sliced data is routed to the HDB3/B3ZS Decoder, during which the original data content as transmitted
by the Remote Terminal Equipment is restored to its original content.
Outputs the recovered clock and data to the Local Terminal Equipment in the form of CMOS level signals via
the RPOS, RNEG, RCLK1 and RCLK2 output pins.
THE MICROPROCESSOR SERIAL INTERFACE
The XRT73LC00A can be configured to operate in either the Hardware Mode or the HOST Mode.
The Hardware Mode
Connect the HOST/HW input pin (pin 18) to GND to configure the XRT73LC00A to operate in the Hardware
Mode.
When the XRT73LC00A is operating in the Hardware Mode, the following is true:
1. The Microprocessor Serial Interface block is
disabled.
2. The XRT73LC00A is configured via input pin settings.
Each of the pins associated with the Microprocessor Serial Interface takes on their alternative role as defined
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相關代理商/技術參數(shù)
參數(shù)描述
XRT73LC00IV 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73LC03A 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73LC03A_08 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73LC03AES 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT73LC03AIV 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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