參數資料
| 型號： | XRT73LC00AIVTR-F |
| 廠商： | Exar Corporation |
| 文件頁數： | 4/61頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU STS1/DS3/E3 SGL 44TQFP |
| 標準包裝： | 1,000 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數： | 1/1 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應商設備封裝： | 44-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
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XRT73LC00A
9
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
30
LCV/(RCLK2)
O
Line Code Violation Indicator/Receive Clock Output pin 2:
The function of this pin depends upon whether the XRT73LC00A is operating in
the HOST Mode, the Hardware Mode or User selection.
HOST Mode - Line Code Violation Indicator Output:
If the XRT73LC00A is configured to operate in the HOST Mode, then this pin
functions as the LCV output pin by default. However, by using the on-chip Com-
mand Registers, this pin can be configured to function as the second Receive
Clock signal output pin RCLK2.
Hardware Mode - Receive Clock Output pin 2:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT73LC00A outputs data via the RPOS and RNEG out-
put pins on the rising edge of this clock signal.
NOTE:
If the XRT73LC00A is operating in the HOST Mode and this pin is
configured to function as the additional Receive Clock signal output pin,
then the XRT73LC00A can be configured to update the data on the
RPOS and RNEG output pins on the falling edge of this clock signal.
31
RCLK1
O
Receive Clock Output pin 1:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT73LC00A outputs data via the RPOS and RNEG out-
put pins on the rising edge of this clock signal.
NOTE: If the XRT73LC00A is operating in the HOST Mode, the device can be
configured to update the data on the RPOS and RNEG output pins on
the falling edge of this clock signal.
32
RNEG
O
Receive Negative Pulse Output:
This output pin pulses “High” whenever the XRT73LC00A has received a Nega-
tive Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
NOTES:
1.
If the B3ZS/HDB3 Decoder is enabled, the zero suppression patterns in
the incoming line signal (such as: "00V", "000V", "B0V", "B00V") are not
reflected at this output.
2.
This output pin is inactive if the XRT73LC00A has been configured to
operate in the Single-Rail Mode.
33
RPOS
O
Receive Positive Pulse Output:
This output pin pulses “High” whenever the XRT73LC00A has received a Posi-
tive Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
NOTE: If the B3ZS/HDB3 Decoder is enabled, the zero suppression patterns in
the incoming line signal (such as: "00V", "000V", "B0V", "B00V") are not
reflected at this output.
34
ICT
I
In-Circuit Test Input:
Setting this input pin “Low” causes all digital and analog outputs to go into a
high-impedance state in order to permit in-circuit testing. Set this pin “High” for
normal operation.
NOTE: This pin is internally pulled “High”.
PIN DESCRIPTION
PIN #SYMBOL
TYPE
DESCRIPTION
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XRT73LC00IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03A | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03A_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03AES | 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73LC03AIV | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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