參數(shù)資料
型號(hào)： XRT7300IVTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 3/55頁(yè)
文件大小： 0K
描述： IC LIU E3/DS3/STS-1 SGL 44TQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： DS3，E3，STS-1
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 44-LQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 帶卷 (TR)
XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.2
7
27
EXCLK
I
External Reference Clock Input:
Apply a 34.368MHz clock signal for E3 applications, a 44.736 MHz clock signal
for DS3 applications or a 51.84 MHz clock signal for SONET STS-1 applications.
28
GND
****
Receiver Digital Ground
29
VDD
****
Receiver Digital VDD
30
LCV/(RCLK2)
O
Line Code Violation Indicator/Receive Clock Output pin 2:
The function of this pin depends upon whether the XRT7300 is operating in the
HOST Mode, the Hardware Mode or User selection.
HOST Mode - Line Code Violation Indicator Output:
If the XRT7300 is configured to operate in the HOST Mode, then this pin func-
tions as the LCV output pin by default. However, by using the on-chip Command
Registers, this pin can be configured to function as the second Receive Clock
signal output pin (RCLK2).
Hardware Mode - Receive Clock Output pin 2:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT7300 outputs data via the RPOS and RNEG output
pins on the rising edge of this clock signal.
NOTE: If the XRT7300 is operating in the HOST Mode and this pin is configured
to function as the additional Receive Clock signal output pin, then the XRT7300
can be configured to update the data on the RPOS and RNEG output pins on the
falling edge of this clock signal.
31
RCLK1
O
Receive Clock Output pin 1:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT7300 outputs data via the RPOS and RNEG output
pins on the rising edge of this clock signal.
NOTE: If the XRT7300 device is operating in the “Host” Mode, then the user can
configure the device to update the data on the RPOS and RNEG output pins on
the falling edge of this clock signal.
32
RNEG
O
Receive Negative Pulse Output:
This output pin pulses “High” whenever the XRT7300 has received a Negative
Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
NOTE: If the B3ZS/HDB3 Decoder is enabled, then the zero suppression pat-
terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not
reflected at this output.
33
RPOS
O
Receive Positive Pulse Output:
This output pin pulses “High” whenever the XRT7300 has received a Positive
Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
NOTE: If the B3ZS/HDB3 Decoder is enabled, then the zero suppression pat-
terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not
reflected at this output.
34
ICT
I
In-Circuit Test Input:
Setting this pin “Low” causes all digital and analog outputs to go into a high-
impedance state to allow for in-circuit testing. This pin is internally pulled “High”.
PIN DESCRIPTION
PIN #SYMBOL
TYPE
DESCRIPTION
相關(guān)PDF資料
PDF描述
VI-21X-MX-F1 CONVERTER MOD DC/DC 5.2V 75W
VI-B62-IV-F3 CONVERTER MOD DC/DC 15V 150W
VI-B5F-MX-B1 CONVERTER MOD DC/DC 72V 75W
XRT75R03DIVTR IC LIU E3/DS3/STS-1 3CH 128LQFP
VI-21V-MX-F2 CONVERTER MOD DC/DC 5.8V 75W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT7302IV 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver
XRT73L00 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L00A 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L00AES 功能描述:界面開(kāi)發(fā)工具 Eval System for XRT73L00A Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
XRT73L00AIV 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝

我的聯(lián)系方式

*
*
*