參數資料
| 型號： | XRT7300IVTR-F |
| 廠商： | Exar Corporation |
| 文件頁數： | 2/55頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 SGL 44TQFP |
| 標準包裝： | 1,000 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數： | 1/1 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應商設備封裝： | 44-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
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XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.2
6
20
SDO/(LCV)
O
Serial Data Output from the Controller Port/(Line Code Violation Output
(LCV) Indicator.):
The function of this input pin depends upon whether the XRT7300 is operating in
the HOST or the Hardware Mode.
HOST Mode - Microprocessor Serial Interface - Serial Data Output.
This pin serially outputs the contents of the specified Command Register during
Read Operations. The data on this pin is updated on the falling edge of the
SCLK input signal. This pin is tri-stated upon completion of data transfer.
Hardware Mode - Line Code Violation Output Indicator.
This pin pulses “High” for one bit period any time the Receive Section of the
XRT7300 detects a Line Code Violation in the incoming E3, DS3 or STS-1 Data
Stream.
21
SCLK/(ENCO-
DIS)
I
Microprocessor Serial Interface Clock Signal/Encoder Disable:
HOST Mode - Microprocessor Serial Interface Clock Signal
This signal is used to sample the data on the SDI pin on the rising edge of this
signal. Additionally, during Read operations the Microprocessor Serial Interface
updates the SDO output on the falling edge of this signal.
Hardware Mode - B3ZS/HDB3 Encoder Disable
Setting this input pin “High” disables the B3ZS/HDB3 Encoder and configures
the XRT7300 to transmit the line signal in an AMI Format.
Setting this input pin “Low” enables the B3ZS/HDB3 Encoder and configures the
XRT7300 to transmit the line signal in the B3ZS format (for DS3/STS-1 opera-
tion) or in the HDB3 format (for E3 operation).
22
CS/(DECODIS)
I
Microprocessor Serial Interface - Chip Select/Decoder Disable
The function of this input pin depends upon whether the XRT7300 is operating in
the HOST or the Hardware Mode.
HOST Mode - Chip Select Input:
The Local Microprocessor must assert this pin (e.g., set it to “0”) in order to
enable communication with the XRT7300 via the Microprocessor Serial Inter-
face.
Hardware Mode - (B3ZS/HDB3 Decoder Disable)
Setting this input pin “High” disables the B3ZS/HDB3 Decoder. Setting this input
pin “Low” enables the B3ZS/HDB3 Decoder.
23
RLOL
O
Receive Loss of Lock Output Indicator
This output pin toggles “High” if the XRT7300 has detected a Loss of Lock Con-
dition. The XRT7300 declares an LOL (Loss of Lock) Condition if the recovered
clock frequency deviates from the Reference Clock frequency (available at the
EXCLK input pin) by more than 0.5%.
24
RLOS
O
Receive Loss of Signal Output Indicator
This output pin toggles “High” if the XRT7300 has detected a Loss of Signal
Condition in the incoming line signal.
The criteria the XRT7300 uses to declare an LOS Condition depends upon
whether the device is operating in the E3 or DS3/STS-1 Mode.
25
GND
****
Digital GND
26
VDD
****
Digital VDD
PIN DESCRIPTION
PIN #SYMBOL
TYPE
DESCRIPTION
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