
xr
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L52
REV. 1.0.1
III
T
X
DS3 M-B
IT
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
35)...................................................................................89
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
1 (A
DDRESS
= 0
X
36).................................................................................89
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
2 (A
DDRESS
= 0
X
37).................................................................................90
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
3 (A
DDRESS
= 0
X
38).................................................................................90
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
4 (A
DDRESS
= 0
X
39).................................................................................91
2.3.6 Transmit E3 (ITU-T G.832) Configuration Registers.............................................................................. 91
T
X
E3 C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
30)................................................................................91
T
X
E3 LAPD C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
33) .....................................................................92
T
X
E3 LAPD S
TATUS
AND
I
NTERRUPT
R
EGISTER
(A
DDRESS
= 0
X
34)..........................................................93
T
X
E3 GC B
YTE
R
EGISTER
(A
DDRESS
= 0
X
35)..........................................................................................94
T
X
E3 MA B
YTE
R
EGISTER
(A
DDRESS
= 0
X
36)..........................................................................................94
T
X
E3 MA B
YTE
R
EGISTER
(A
DDRESS
= 0
X
36)..........................................................................................95
T
X
E3 NR B
YTE
R
EGISTER
(A
DDRESS
= 0
X
37) ..........................................................................................95
T
X
E3 TTB-0 R
EGISTER
(A
DDRESS
= 0
X
38)...............................................................................................95
T
X
E3 TTB-1 R
EGISTER
(A
DDRESS
= 0
X
39)...............................................................................................96
T
X
E3 TTB-2 R
EGISTER
(A
DDRESS
= 0
X
3A)..............................................................................................96
T
X
E3 TTB-3 R
EGISTER
(A
DDRESS
= 0
X
3B)..............................................................................................96
T
X
E3 TTB-4 R
EGISTER
(A
DDRESS
= 0
X
3C)..............................................................................................97
T
X
E3 TTB-5 R
EGISTER
(A
DDRESS
= 0
X
3D)..............................................................................................97
T
X
E3 TTB-6 R
EGISTER
(A
DDRESS
= 0
X
3E)..............................................................................................98
T
X
E3 TTB-7 R
EGISTER
(A
DDRESS
= 0
X
3F) ..............................................................................................98
T
X
E3 TTB-8 R
EGISTER
(A
DDRESS
= 0
X
40)...............................................................................................98
T
X
E3 TTB-9 R
EGISTER
(A
DDRESS
= 0
X
41)...............................................................................................99
T
X
E3 TTB-10 R
EGISTER
(A
DDRESS
= 0
X
42).............................................................................................99
T
X
E3 TTB-11 R
EGISTER
(A
DDRESS
= 0
X
43).............................................................................................99
T
X
E3 TTB-12 R
EGISTER
(A
DDRESS
= 0
X
44)...........................................................................................100
T
X
E3 TTB-13 R
EGISTER
(A
DDRESS
= 0
X
45)...........................................................................................100
T
X
E3 TTB-14 R
EGISTER
(A
DDRESS
= 0
X
46)...........................................................................................101
T
X
E3 TTB-15 R
EGISTER
(A
DDRESS
= 0
X
47)...........................................................................................101
T
X
E3 FA1 E
RROR
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
48) ..........................................................................101
T
X
E3 FA2 E
RROR
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
49) ..........................................................................102
T
X
E3 BIP-8 E
RROR
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
4A)........................................................................102
2.3.7 Transmit E3 Framer Configuration Registers (ITU-T G.751) ............................................................... 102
T
X
E3 C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
30)..............................................................................102
T
X
E3 LAPD C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
33) ...................................................................104
T
X
E3 LAPD S
TATUS
AND
I
NTERRUPT
R
EGISTER
(A
DDRESS
= 0
X
34)........................................................105
T
X
E3 S
ERVICE
B
ITS
R
EGISTER
(A
DDRESS
= 0
X
35)..................................................................................105
T
X
E3 FAS E
RROR
M
ASK
R
EGISTER
- 0 (A
DDRESS
= 0
X
48).....................................................................106
T
X
E3 FAS E
RROR
M
ASK
R
EGISTER
- 1 (A
DDRESS
= 0
X
49).....................................................................106
T
X
E3 BIP-4 E
RROR
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
4A)........................................................................106
2.3.8 Performance Monitor Registers............................................................................................................ 107
PMON LCV E
VENT
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
51) ............................................................107
PMON F
RAMING
B
IT
/B
YTE
E
RROR
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
52).....................................107
PMON F
RAMING
B
IT
/B
YTE
E
RROR
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
53)......................................108
PMON P
ARITY
E
RROR
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
54).......................................................108
PMON P
ARITY
E
RROR
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
55)........................................................108
PMON FEBE E
VENT
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
56).........................................................108
PMON FEBE E
VENT
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
57)..........................................................109
PMON CP-B
IT
E
RROR
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
58).......................................................109
PMON CP-B
IT
E
RROR
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
59)........................................................109
PMON H
OLDING
R
EGISTER
(A
DDRESS
= 0
X
6C)......................................................................................110
O
NE
-S
ECOND
E
RROR
S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
6D)..................................................................110
LCV - O
NE
-S
ECOND
A
CCUMULATOR
R
EGISTER
- MSB (A
DDRESS
= 0
X
6E)..............................................110
LCV - O
NE
-S
ECOND
A
CCUMULATOR
R
EGISTER
- LSB (A
DDRESS
= 0
X
6F)...............................................111
F
RAME
P
ARITY
E
RRORS
- O
NE
-S
ECOND
A
CCUMULATOR
R
EGISTER
- MSB (A
DDRESS
= 0
X
70) .................111