參數(shù)資料
型號: XRD98L62ACV
廠商: EXAR CORP
元件分類: 消費家電
英文描述: CCD Image Digitizers with CDS, PGA and 12-Bit A/D
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48
文件頁數(shù): 32/37頁
文件大?。?/td> 286K
代理商: XRD98L62ACV
XRD98L62
32
Rev. P2.00
Preliminary
End of Line N
Start of Line N+1
Active Video
Pixels
OB pixels
Vertical Shift
Dummy &
OB pixels
CAL
Internal
DC restore time
CCD
Signal
Active Video pixels
t
CAL
4 pixels
CLAMP
(vertical shift)
Disconnect CDS from
input pins
Internal Black Level
calibration time
t
CAL
- 4 pixels
Minimum 5 Pixels
Figure 22. Line Rate Timing with OneShot=1 & VSreject=1
Setting Power and Performance with Rext
The power and performance levels of the XRD98L62
are set by the value of Rext. Rext sets the current bias
level for the entire chip. Rext is connected between
pin 39 (ExtRef) and analog ground (see Figure 23).
This resistor should be placed as close as possible to
the pin and routed directly to a ground plane in a PCB
layout. A surface mount carbon resistor is recom-
mended.
Increasing values of Rext decrease the power, linearity
and noise performance of the XRD98L62. Lowering the
value of Rext increases linearity and noise perfor-
mance while increasing power. The tested default
value for Rext is 20KOhms.
In order to match system to system performance and
set consistent manufacturable performance levels
between cameras, it is recommended that the Rext
resistor have <1% tolerance.
相關(guān)PDF資料
PDF描述
XRD98L62 CCD Image Digitizers with CDA,PGS and 12-Bit A/D(CCD圖像數(shù)字轉(zhuǎn)換器(帶CDA,PGS和12位A/D轉(zhuǎn)換器))
XRDAN28 Frequency Response Effects of Overampling and Averaging on A/D Output Data
XRDAN29 Criteria for Accurate Sampling of Analog Signals
XRDAN30 CMOS Current Output D/A Converter Design Concepts for Wide Bandwidth Applications
XRK32308_07 3.3V ZERO DELAY BUFFER
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