參數(shù)資料
型號(hào)： XRD98L62ACV
廠商： EXAR CORP
元件分類： 消費(fèi)家電
英文描述： CCD Image Digitizers with CDS, PGA and 12-Bit A/D
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48
文件頁(yè)數(shù)： 28/37頁(yè)
文件大?。?/td> 286K
代理商： XRD98L62ACV
XRD98L62
28
Rev. P2.00
Preliminary
Figure 17. Pixel Rate Clock Timing with RSTreject=1
CCD Signal
SBLK
SPIX
ADCLK
Reset Reject
Switches Turn OFF
Video
Level
φ
3
Black
Level
Aperture delays
One of the most difficult tasks in designing a digital
camera is optimizing the pixel timing for the CCD, CDS
and ADC. We have included the programmable aper-
ture delay function to help simplify this job.
There are two serial interface registers, DelayA &
DelayB, used to program the aperture delays. Each
register is divided into 3 delay parameters. Each delay
parameter is 3 bits wide. Each delay parameter can be
set to add from 0ns to 7ns of delay.
The delays are added to the clock signals after the
polarity control. This means the definition of leading
edge and trailing edge depends on the polarity control
bit for each clock. For the default case, SBLKpol=0 &
SPIXpol=0, the leading edge is the falling edge and the
trailing edge is the rising edge.
DelayA[2:0] controls the delay added to the leading
edge of SBLK. This positions the falling edge of
internal signal
φ
1.
DelayA[5:3] controls the delay added to the trailing
edge of SBLK. This positions the rising edge of
internal signal
φ
1.
DelayB[2:0] controls the delay added to the leading
edge of
φ
2. This positions the falling edge of internal
signal
φ
2.
DelayB[5:3] controls the delay added to the trailing
edge of SPIX. This positions the rising edge of
internal signal
φ
2.
DelayB[8:6] is only used when SPIXopt=0. It controls
the delay from the trailing edge of SBLK to the start
of the internal
φ
2 control. This delay is in addition to
DelayA[5:3], the SBLK trailing edge delay.
DelayA[8:6] controls the delay added to ADCLK. This
is a simple delay, it adds the same delay to both the
rising and falling edges of ADCLK to create
φ
4.
相關(guān)PDF資料
PDF描述
XRD98L62 CCD Image Digitizers with CDA，PGS and 12-Bit A/D(CCD圖像數(shù)字轉(zhuǎn)換器（帶CDA，PGS和12位A/D轉(zhuǎn)換器）)
XRDAN28 Frequency Response Effects of Overampling and Averaging on A/D Output Data
XRDAN29 Criteria for Accurate Sampling of Analog Signals
XRDAN30 CMOS Current Output D/A Converter Design Concepts for Wide Bandwidth Applications
XRK32308_07 3.3V ZERO DELAY BUFFER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRD98L62ACV-F 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
XRD98L62EVAL 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 XRD98L62 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
XRD98L62ZEVAL 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Eval Board (Solder) XRD98L62AIV RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
XRD98L63 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D
XRD98L63AIV 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D
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