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參數(shù)資料
| 型號(hào)： | XRD98L62ACV |
| 廠商： | EXAR CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48 |
| 文件頁(yè)數(shù)： | 16/37頁(yè) |
| 文件大小： | 286K |
| 代理商： | XRD98L62ACV |
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XRD98L62
16
Rev. P2.00
Preliminary
RBenable RBreg
8
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RBreg
7
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
RBreg
6
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
RBreg
5
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
x
x
x
Rbreg
4
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
x
x
x
RBreg
3
x
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
x
x
x
RBreg
2
x
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
x
x
x
RBreg
1
x
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
x
x
x
RBreg
0
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
x
x
x
Selected Register
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
none (ADC data output)
Gain
Offset
Calibration
Wait A
Wait B
OB Lines
CDAC
FDAC
Control
Polarity
Clock
Delay A
Delay B
DAC0
DAC1
ReadBack
Reset
FDAC output from Cal. logic
CDAC output from Cal. logic
Avg. output from Cal logic
Serial Interface Read Back
The readback function is used to view the content of
the serial interface registers as well as several key
registers in the calibration logic. Readback is enabled
by writing a 1 to the RBenable bit of the Readback
register, bit D9 of register 62.
In the readback mode, the content of the selected
register is output on the 10 MSBs of the ADC output
bus pins DB[11:2]. As long as valid clocks and CCD
signal are applied, the calibration will continue to
function properly during readback (internally the ADC
data is still sent to the calibration logic).
Registers are selected for readback by writing to the
RBreg[8:0] bits in the Readback register, bits D8 to D0
of register 62. If RBreg[8:6]=000, then RBreg[5:0] are
used to address the serial interface registers. Cur-
rently only register addresses 0 to 14, 62 and 63 are
defined. If RBreg[8:6]
≠
000, then RBreg[5:0] are ig-
nored and RBreg[8:6] are used to address registers in
the calibration logic. Currently only three calibration
registers are accessible.
Table 2. Read-back Register Selection
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| XRDAN28 | Frequency Response Effects of Overampling and Averaging on A/D Output Data |
| XRDAN29 | Criteria for Accurate Sampling of Analog Signals |
| XRDAN30 | CMOS Current Output D/A Converter Design Concepts for Wide Bandwidth Applications |
| XRK32308_07 | 3.3V ZERO DELAY BUFFER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRD98L62ACV-F | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRD98L62EVAL | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 XRD98L62 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRD98L62ZEVAL | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Eval Board (Solder) XRD98L62AIV RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRD98L63 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L63AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
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