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參數(shù)資料
| 型號： | XRD98L62ACV |
| 廠商： | EXAR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48 |
| 文件頁數(shù)： | 30/37頁 |
| 文件大?。?/td> | 286K |
| 代理商： | XRD98L62ACV |
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XRD98L62
30
Rev. P2.00
Preliminary
Line Rate Clocks
CLAMP & CAL are the two line rate clock signals.
There are two modes of operation for these clocks.
CAL & CLAMP Mode
In this mode the CLAMP signal is used to activate the
DC restore Clamp at the CDS input, and the CAL signal
is used to define the Optical Black pixels to be used for
the Black Level calibration function. Typically the
CLAMP pulse comes during the dummy or optical
black pixels at the beginning of each scan line, and the
CAL pulse comes during the longer string of optical
black pixels at the end of each scan line. CLAMP &
CAL must not be active at the same time.
In this mode there is an option to disconnect the CDS
from the input pins during the Vertical Shift time. To
enable this option write a “1” to the VSreject bit in the
Clock register. To properly define the Vertical Shift time
you must set the ClampCal bit properly.
In the typical case, the CCD has a few OB pixels at the
beginning of a line (CLAMP time) and a larger number
of OB pixels at the end of a scan line (CAL time). In this
case set the ClampCal bit = 0, this will define the
Vertical shift time as the time from the end of the CAL
pulse to the beginning of the CLAMP pulse.
If a CCD has more OB pixels at the beginning of a line,
then CAL should be active during these pixels and
CLAMP should be active at the end of the line. In this
case, set the ClampCal bit = 1, this will define the
Vertical shift time as the time from the end of the
CLAMP pulse to the beginning of the CAL pulse.
The ClampCal bit is also used by the Calibration logic.
If ClampCal is set as defined above, it should be correct
for the Calibration logic as well.
End of Line N
Start of Line N+1
Active Video
Pixels
OB pixels
Vertical Shift
Dummy &
OB pixels
CAL
(Black Level)
CLAMP
(DC restore)
CCD
Signal
Active Video pixels
t
CAL
t
CLAMP
Vert. Shift Reject
(internal)
Disconnect CDS from
input pins
Figure 20. Line Rate Timing with OneShot=0, VSreject=1 & ClampCal=0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRD98L62ACV-F | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRD98L62EVAL | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 XRD98L62 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRD98L62ZEVAL | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 Eval Board (Solder) XRD98L62AIV RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRD98L63 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L63AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
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