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參數(shù)資料
| 型號(hào)： | XR88C681P/40-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 88/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART CMOS DUAL 40PDIP |
| 標(biāo)準(zhǔn)包裝： | 9 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 1 字節(jié)，3 字節(jié) |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 帶并行端口： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 40-PDIP |
| 包裝： | 管件 |
| 其它名稱： | 1016-1640 XR88C681P/40-F-ND |
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XR88C681
87
Rev. 2.11
Receiver Operation During Multi-Drop Mode
When a channel has been programmed into the
Multi-Drop Mode, and the Receiver has been disabled (a
typical configuration), the Receiver will load a character
into the RHR and set the RXRDY indicator (and/or
interrupt) if the A/D bit is “1” (Address flag). However, the
character will be discarded if its A/D bit is “0” (Data flag).
Therefore, in response to the RXRDY indicator, the CPU
should then read the received character and determine if
the address that it represents matches that of the CPU. If
the Addresses do match, (indicating that it is the Target
Slave), then the CPU should enable the Receiver, in
preparation for the subsequent blocks of data.
Once the Receiver has been enabled the Receiver Serial
Data will be processed as in Normal Operation. The
received characters are accessible to the CPU by reading
the RHR. The state of the A/D flag bit is available at
SRn[5], the Status Register bit normally used to indicate
“Parity Error”. Therefore, in conjunction with receiver
each new character, the CPU should continue to monitor
SRn[5] in order to verify that it is a “0” (Data characters).
Once the “Target CPU” detects a new address character,
SRn[5] =“1”, it should compare this address with its own.
If the addresses do not match, then this CPU is not the
intended recipient of the next block of data, and now
should disable the Receiver.
Figure 49 presents a flow
diagram depicting a recommended procedure for
handling received characters while in the Multi-Drop
Mode.
START
Receiver is Disabled
Channel is Commanded
into Multi-Drop Mode.
MR1n[4:3] = [1, 1]
Reject Character
Receiver remains Disabled
Read in Address
Character from RHRn
Has
RXRDY Indicator
been asserted
?
No
Yes
No
Enable Receiver
(Write x2h to the
Appropriate Channel
Command Register)
Read in Data Character
from RHR.
Check SRn[5]
Does
Newly Received
Address match
CPU Address
?
Is the
New Character a
Data Character
SRn[5] = 1?
Yes
No
Figure 49. A Flow Diagram Depicting a Procedure That Can Be Used to Receive
Characters in the Multi-Drop Mode.
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