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參數(shù)資料
| 型號： | XR88C681P/40-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 10/101頁 |
| 文件大小： | 0K |
| 描述： | IC UART CMOS DUAL 40PDIP |
| 標(biāo)準(zhǔn)包裝： | 9 |
| 特點： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 1 字節(jié)，3 字節(jié) |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 帶并行端口： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 40-PDIP |
| 包裝： | 管件 |
| 其它名稱： | 1016-1640 XR88C681P/40-F-ND |
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XR88C681
16
Rev. 2.11
appropriate data to the appropriate channel’s Command Register. Therefore, both Mode Registers, within a given
channel, have the same logical address. The features and functions of the DUART that are controlled by the Mode
Registers are discussed in detail in
Section G.3.
B.2 Command Decoding
Each channel is equipped with a Command Register. In general, the role of these Command Registers are to
enable/disable the Transmitter, enable/disable the Receiver, along with facilitating a series of other miscellaneous
commands. The bit format for each Command Register is presented herewith.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Miscellaneous Commands
Enable/Disable
Receiver
Enable/Disable
Transmitter
See Following Text
00 = No Change
01 = Enable Rx
10 = Disable Rx
11 = Not valid (do not use)
00 = No Change
01 = Enable Tx
10 = Disable Tx
11 = Not Valid (Do not use)
Table 2. (CRA, CRB) Bit Format for Command Registers of Channels A & B
The function of the lower nibble of the Command Registers is fairly straight-forward. This nibble is used to either enable
or disable the Transmitter and/or Receiver.
The upper nibble of the Command Register is used to invoke a series of miscellaneous commands.
Table 3 defines the
commands associated with the upper nibble of the Command Registers.
Please note that the upper nibble commands
116 through B16 effects only the performance of Command Register’s Channel. However, commands C16 and D16
effects system (or chip) level operation.
Bit 7
Bit 6
Bit 5
Bit 4
Description
0
Null Command.
0
1
Reset MRn Pointer.
Causes the Channel’s MRn
pointer to point to MR1n.
0
1
0
Reset Receiver.
Reset the individual channel re-
ceiver as if a Hardware Reset has been applied.
The Receiver is disabled and the FIFO is flushed.
0
1
Reset Transmitter.
Resets the individual channel
transmitter as if a Hardware Reset had been applied.
The TXDn output is forced to a high level.
Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers,
Unless Otherwise Specified (Cont’d Next Page)
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