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參數(shù)資料
| 型號： | XR68C192IP |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER |
| 中文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 282K |
| 代理商： | XR68C192IP |
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XR68C92/192
21
Rev. P1.10
OP3 output select
0 0 = The complement of OPR
0 1 = C/T Output 1
1 0 = TxBClk1-Transmit B 1X clock
1 1 = RxBClk1- Receive B 1X clock
If OP3 is to be used for the timer output, Users should
program the counter/timer for timer mode (ACR Bit-6
= 1), initialize the counter/timer pre-load registers
(CTUR and CTLR), and the start counter command
issued before setting OPCR Bits 3-2 = 01.
OP4 output select
0 = The complement of OPR
1 = -RxARDY/-RxAFULL
OP5 output select
0 = The complement of OPR
1 = -RxBRDY/-RxBFULL
OP6 output select
0 = The complement of OPR
1 = -TxARDY
OP7 output select
0 = The complement of OPR
1 = -TxBRDY
Output Port Register (OPR)
All bits, unless programmed for alternate function, can
be set high or low individually:
0 = Sets output port high
1 = Sets output port low
For example, setting bit-4 to 1 will set OP4 low.
AUXILIARY CONTROL REGISTER (ACR)
ACR Bits 3-0.
This field selects which bits of the input port change
register (IPCR) cause the input change bit in the
interrupt status register (ISR Bit-7) to be set.
0 = Disabled
1 = Enabled
ACR Bits 6-4.
Counter/Timer Mode and Clock Source. Should only be
altered while the C/T is not in use (stopped if in counter
mode, output and/or interrupt masked if in timer mode).
MODE
CLOCK
SOURCE
0 0 0
0 0 1
0 1 0
0 1 1
Counter
Counter
Counter
Counter
External (IP2)
TXAClk1-Transmit A 1X clock
TXBClk1-Transmit B 1X clock
Crystal or External Clock
(XTAL1/Clk) Divided by 16
External (IP2)
External (IP2) Divided by 16
Crystal or External Clock
(XTAL1/Clk)
Crystal or External Clock
(XTAL1/Clk) Divided by 16
1 0 0
1 0 1
1 1 0
Timer
Timer
Timer
1 1 1
Timer
ACR Bit-7
Baud rate table Select. Should only be changed after
both channels have been reset and are disabled.
0 = Set 1
1 = Set 2
INPUT PORT CHANGE REGISTER (IPCR)
IP Level Bits 3-0.
0 = Low
1 = High
IP Delta Bits 7-4.
0 = No
1 = Yes
INTERRUPT STATUS REGISTER (ISR)
This register provides the status of all potential interrupt
sources. The contents of this register are logically
“AND”-ed with the contents of the interrupt mask regis-
ter, and the results are "NOR"-ed to produce the -INT
output. All active interrupt sources are visible by reading
the ISR, regardless of the contents of the interrupt mask
register. Reading the ISR has no effect on any interrupt
source. Each active interrupt source must be cleared in
a source-specific fashion to clear the ISR. All interrupt
sources are cleared when the XR68C92/192 is reset.
4
ISR Bit-0.
Transmit ready A. This bit is the channel A equivalent of
ISR Bit-4.
ISR Bit-1.
Receive ready A or FIFO full.
The function of this bit is
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR68C192IV | DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER |
| XR68C92 | DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER |
| XR68C92CJ | DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER |
| XR68C92CP | DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER |
| XR68C92CV | DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR68C192IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER |
| XR68C192IV-F | 功能描述:UART 接口集成電路 Dual Channel UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR68C681 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CMOS Dual Channel UART (DUART) |
| XR68C681CJ | 制造商:EXAR 制造商全稱:EXAR 功能描述:CMOS Dual Channel UART (DUART) |
| XR68C681CJ44 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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