REV. 1.0.2 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 2.13 Auto Xon/Xoff (Software) Flow Control
參數(shù)資料
型號: XR20V2172IL64-F
廠商: Exar Corporation
文件頁數(shù): 9/51頁
文件大小: 0K
描述: IC UART/TXRX I2C/SPI RS232 64QFN
標準包裝: 260
特點: *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232
電源電壓: 2.97 V ~ 3.63 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應商設備封裝: 64-QFN(9x9)
包裝: 托盤
XR20V2172
17
REV. 1.0.2
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
2.13
Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 15), the V2172 compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the V2172 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the V2172 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the V2172 will resume operation
and clear the flags (ISR bit-4).
Upon power-up, the contents of the Xon/Xoff 8-bit flow control registers to 0x00. The user can write any Xon/
Xoff value desired for software flow control. These registers are not reset by a hardware or software reset.
Different conditions can be set to detect Xon/Xoff characters (See Table 15) and suspend/resume
transmissions. When double 8-bit Xon/Xoff characters are selected, the V2172 compares two consecutive
receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX
transmissions accordingly. Under the above described flow control mechanisms, flow control characters are
not placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the V2172 automatically
sends the Xoff-1,2 via the serial TX output to the remote modem when the RX FIFO reaches the Halt Level
(TCR[3:0]). To clear this condition, the V2172 will transmit the programmed Xon-1,2 characters as soon as RX
FIFO falls down to the Resume Level.
2.14
Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The V2172 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will
be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal
Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of
character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the special character comparison.
2.15
Sleep Mode with Auto Wake-Up
The V2172 supports low voltage system designs, hence, a sleep mode is included to reduce its power
consumption when the chip is not actively used. In the Partial Sleep mode, the internal oscillator of the UART
or charge pump of the RS-232 transceiver is turned off to reduce the power consumption. In the Full Sleep
mode, both the oscillator and the charge pump are turned off.
2.15.1
Partial Sleep Mode
There are two different partial sleep modes. In the first mode, the UART is in sleep mode and the charge pump
is active. In the other mode, the UART is still active but the charge pump is turned off.
2.15.1.1
UART in sleep mode, RS-232 transceiver active
If the ACP pin is LOW, then the charge pump for the RS-232 transceiver will always be active. But the UART
portion in the V2172 can still enter sleep mode if all of these conditions are satisfied for both channels:
no interrupts pending (ISR bit-0 = 1)
the 16-bit divisor programmed in DLM and DLL registers is a non-zero value
sleep mode is enabled (IER bit-4 = 1)
modem inputs are not toggling (MSR bits 0-3 = 0)
RXD input pin is idling LOW
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