REV. 1.0.2 MCR[2]: OP1# / TCR and TLR Enable OP1# is not availabl" />
參數(shù)資料
型號(hào)： XR20V2172IL64-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 24/51頁(yè)
文件大?。?/td> 0K
描述： IC UART/TXRX I2C/SPI RS232 64QFN
標(biāo)準(zhǔn)包裝： 260
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232
電源電壓： 2.97 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-QFN（9x9）
包裝： 托盤(pán)
XR20V2172
30
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.2
MCR[2]: OP1# / TCR and TLR Enable
OP1# is not available as an output pin on the V2172. But it is available for use during Internal Loopback Mode
(MCR[4] = 1). In the Internal Loopback Mode, this bit is used to write the state of the modem RI# interface
signal.
This bit is also used to select between the MSR and TCR registers at address offset 0x6 and the SPR and TLR
registers at address offset 0x7. Table 12 and Table 13 below shows how these registers are accessed.
TABLE 12: REGISTER AT ADDRESS OFFSET 0X6
EFR[4] MCR[2] Register at Address Offset 0x6
0
X
Modem Status Register (MSR)
1
0
Modem Status Register (MSR)
1
Trigger Control Register (TCR)
TABLE 13: REGISTER AT ADDRESS OFFSET 0X7
EFR[4] MCR[2] Register at Address Offset 0x7
0
X
Scratchpad Register (SPR)
1
0
Scratchpad Register (SPR)
1
Trigger Level Register (TLR)
MCR[3]: OP2# Output
OP2# is not available as an output on the V2172 but can be controlled in internal loopback mode.
Logic 0 = OP2# output set HIGH(default).
Logic 1 = OP2# output set LOW.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 14.
MCR[5]: Xon-Any Enable (requires EFR bit-4=1 to write to this bit)
Logic 0 = Disable Xon-Any function (default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the V2172 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable
Logic 0 = Enable the standard modem receive and transmit input/output interface (default).
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface requirement.
While in this mode, the infrared TX output will be idling LOW. SEE”INFRARED MODE (UART CHANNEL B
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