TABLE 5: IRQ# PIN O
參數(shù)資料
型號(hào)： XR20V2172IL64-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 2/51頁(yè)
文件大?。?/td> 0K
描述： IC UART/TXRX I2C/SPI RS232 64QFN
標(biāo)準(zhǔn)包裝： 260
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232
電源電壓： 2.97 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-QFN（9x9）
包裝： 托盤(pán)
TABLE 5: IRQ# PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
IRQ# Pin
HIGH = no data
LOW = 1 byte
HIGH = FIFO below trigger level
LOW = FIFO above trigger level
XR20V2172
10
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.2
2.6
Crystal Oscillator or External Clock Input
The V2172 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in
each of the UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the
output. Please note that the input XTAL1 is not 5V tolerant and so the maximum at the pin should be VCC. For
FIGURE 6. TYPICAL OSCILLATOR CONNECTIONS
C1
22-47 pF
C2
22-47 pF
Y1
1.8432 MHz
to
24 MHz
R1
0-120
(Optional)
R2
500Κ1Μ
XTAL1
XTAL2
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 6). The programmable Baud
Rate Generator is capable of operating with a crystal oscillator frequency of up to 24 MHz. Although the V2172
can accept an external clock of up to 64MHz, the maximum data rate supported by the RS-232 drivers is
250Kbps. For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR
2.7
Programmable Baud Rate Generator with Fractional Divisor
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to
obtain a 16X, 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the transmitter for
data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the
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