REV. 1.0.1 value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon power-up" />
參數(shù)資料
型號： XR20V2170L40-0A-EB
廠商： Exar Corporation
文件頁數(shù)： 2/49頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR20V2170 40QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR20V2170
10
I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon power-up. Therefore, the BRG must be
programmed during initialization to the operating data rate. The DLL and DLM registers provide the integer part
of the divisor and the DLD register provides the fractional part of the dvisior. The four lower bits of the DLD are
used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud
Rate Generator Registers DLL, DLM and DLD provides the capability for selecting the operating data rate.
Table 6 shows the standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the
pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 6. At 8X
sampling rate, these data rates would double and at 4X sampling rate, these data rates would quadruple. Also,
when using 8X sampling mode, the bit time will have a jitter of ± 1/16 whenever the DLD is non-zero and is an
odd number. When using 4X sampling mode, the bit time will have a jitter of ± 1/8 whenever DLD is non-zero,
odd and not a multiple of 4. When using a non-standard data rate crystal or external clock, the divisor value
can be calculated with the following equation(s):
Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = ’01’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = ’10’
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
DLM = TRUNC(Required Divisor) >> 8
DLL = TRUNC(Required Divisor) & 0xFF
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
The closest divisor that is obtainable in the V2170 can be calculated using the following formula:
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
FIGURE 7. BAUD RATE GENERATOR
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL, DLM and DLD
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X or 8X or 4X
Sampling
Rate Clock
to Transmitter
and Receiver
Fractional Baud
Rate Generator
Logic
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XR20V2170L40-0B-EB 功能描述:UART 接口集成電路 Supports V2170 40pin QFN,SPI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR20V2172 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
XR20V2172_08 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
XR20V2172IL64 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
XR20V2172IL64-F 功能描述:UART 接口集成電路 Transceiver RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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