REV. 1.0.0 I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 1.1.3 SPI Bus Interface The SPI interface consists of four" />
參數(shù)資料
型號(hào): XR20M1280L40-0B-EB
廠商: Exar Corporation
文件頁數(shù): 63/63頁
文件大小: 0K
描述: EVAL BOARD FOR XR20M1280L40
產(chǎn)品培訓(xùn)模塊: XR21V141x Full-Speed USB UART Family
UARTs with Integrated Level Shifters
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,UART
已用 IC / 零件: XR20M1280L40
已供物品:
其它名稱: 1016-1627
XR20M1280
9
REV. 1.0.0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.1.3
SPI Bus Interface
The SPI interface consists of four lines: serial clock (SCL), chip select (CS#), slave output (SO) and slave input
(SI). The serial clock, slave output and slave input can be as fast as 26 Mbps. To access the device in the SPI
mode, the CS# signal for the XR20M1280 is asserted by the SPI master, then the SPI master starts toggling
the SCL signal with the appropriate transaction information. The first bit sent by the SPI master includes
whether it is a read or write transaction and the UART register being accessed. See Table 3 below.
TABLE 3: SPI FIRST BYTE FORMAT
BIT
FUNCTION
7
Read/Write#
Logic 1 = Read
Logic 0 = Write
6
Reserved
5:3
UART Internal Register Address A2:A0
2:1
UART Channel Select
’00’ = UART Channel, other values are reserved
0
Reserved
FIGURE 6. SPI WRITE
R /W
‘0 ’
A 2
A 1
A 0
‘0 ’
X
D 7D 6
D 5D 4
D 3D 2
D 1D 0
SC L
SI
FIGURE 7. SPI READ
R/W ‘0’
A2
A1
A0
‘0’
X
D7
D6
D5
D4
D3
D 2
D1
D0
SCL
SI
SO
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