REV. 1.0.0 I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS ISR[0]: Interrupt Status
參數(shù)資料
型號(hào)： XR20M1280L40-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 27/63頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR20M1280L40
產(chǎn)品培訓(xùn)模塊： XR21V141x Full-Speed USB UART Family
UARTs with Integrated Level Shifters
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
已用 IC / 零件： XR20M1280L40
已供物品： 板
其它名稱(chēng)： 1016-1627
XR20M1280
33
REV. 1.0.0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Table 11).
ISR[4]: Interrupt Status (requires EFR bit-4 = 1)
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff, Xon or special character(s).
ISR[5]: Interrupt Status (requires EFR bit-4 = 1)
ISR bit-5 indicates that CTS# or RTS# has changed state from LOW to HIGH.
ISR[6]: GPIO Interrupt Status
This bit reports the GPIO interrupt status. When a GPIO interrupt has been generated, this bit will be the
inverse of ISR[7]. When the GPIO interrupt is not enabled, this bit will match ISR[7] for 16550 compatibility
ISR[7]: FIFO Enable Status
This bit is set to a logic 0 when the FIFOs are disabled. It is set to a logic 1 when the FIFOs are enabled (See
TABLE 12: FIFO ENABLE STATUS/GPIO INTERRUPT STATUS
FIFO MODE
GPIO INTERRUPT ENABLED
(GPIOINT REGISTER)
GPIO INTERRUPT STATUS
0
FIFO Disabled
No
No GPIO Interrupt
0
FIFO Disabled
Yes
No GPIO Interrupt
0
FIFO Disabled
Yes
GPIO Interrupt
0
1
FIFO Enabled
No
No GPIO Interrupt
1
FIFO Enabled
Yes
No GPIO Interrupt
1
FIFO Enabled
Yes
GPIO Interrupt
1
0
FCR[0]
ISR[7]
ISR[6]
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