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REV. 1.2.2 5V PCI BUS OCTAL UART I TABLE OF CONTENTS GENERAL DESCRIPTION...................................................." />

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參數(shù)資料

型號(hào)：	XR17D158IV-F
廠商：	Exar Corporation
文件頁(yè)數(shù)：	69/73頁(yè)
文件大?。?/td>	0K
描述：	IC UART PCI BUS OCTAL 144LQFP
產(chǎn)品培訓(xùn)模塊：	UART Product Overview
標(biāo)準(zhǔn)包裝：	60
特點(diǎn)：	*
通道數(shù)：	8
FIFO's：	64 字節(jié)
規(guī)程：	RS485
電源電壓：	3.3V，5V
帶自動(dòng)流量控制功能：	是
帶IrDA 編碼器/解碼器：	是
帶故障啟動(dòng)位檢測(cè)功能：	是
帶調(diào)制解調(diào)器控制功能：	是
安裝類型：	表面貼裝
封裝/外殼：	144-LQFP
供應(yīng)商設(shè)備封裝：	144-LQFP（20x20）
包裝：	托盤
其它名稱：	1016-1292

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XR17D158

REV. 1.2.2

5V PCI BUS OCTAL UART

TABLE OF CONTENTS

GENERAL DESCRIPTION................................................................................................. 1

APPLICATIONS ............................................................................................................................................... 1

FEATURES ..................................................................................................................................................... 1

FIGURE 1. BLOCK DIAGRAM ............................................................................................................................................................. 1

FIGURE 2. PIN OUT OF THE DEVICE.................................................................................................................................................. 2

ORDERING INFORMATION

................................................................................................................................2

PIN DESCRIPTIONS .......................................................................................................... 3

FUNCTIONAL DESCRIPTION ........................................................................................... 8

PCI Local Bus Interface............................................................................................................................................... 8

PCI Local Bus Configuration Space Registers ............................................................................................................ 8

EEPROM Interface...................................................................................................................................................... 8

1.0 APPLICATION EXAMPLES .................................................................................................................. 9

TABLE 1: VALID COMBINATIONS OF VCC AND VIO SUPPLY VOLTAGES .............................................................................................. 9

FIGURE 3. TYPICAL APPLICATION FOR A UNIVERSAL ADD-IN CARD .................................................................................................... 9

FIGURE 4. TYPICAL APPLICATIONS IN AN EMBEDDED SYSTEM.......................................................................................................... 10

2.0 XR17D158 REGISTERS ...................................................................................................................... 11

FIGURE 5. THE XR17D158 REGISTER SETS .................................................................................................................................. 11

2.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS .......................................................................... 11

TABLE 2: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ....................................................................................................... 12

2.2 DEVICE CONFIGURATION REGISTER SET ................................................................................................ 13

TABLE 3: XR17D158 DEVICE CONFIGURATION REGISTERS............................................................................................................. 14

TABLE 4: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT ................................................................................... 17

TABLE 5: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT .............................................................................. 17

2.2.1 THE INTERRUPT STATUS REGISTER ..................................................................................................................... 18

FIGURE 6. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3 .................................................................................. 19

TABLE 6: UART CHANNEL [7:0] INTERRUPT SOURCE ENCODING..................................................................................................... 19

TABLE 7: UART CHANNEL [7:0] INTERRUPT CLEARING: .................................................................................................................. 19

2.2.2 GENERAL PURPOSE 16-BIT TIMER/COUNTER [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-

00-00) ............................................................................................................................................................................. 20

FIGURE 7. TIMER/COUNTER CIRCUIT............................................................................................................................................... 20

TABLE 8: TIMER CONTROL REGISTERS ...................................................................................................................................... 20

2.2.3 8XMODE [7:0] (DEFAULT 0X00)................................................................................................................................ 21

2.2.4 REGA [15:8] RESERVED ........................................................................................................................................... 21

2.2.5 RESET [23:16] (DEFAULT 0X00)............................................................................................................................... 21

2.2.6 SLEEP [31:24] (DEFAULT 0X00) ............................................................................................................................... 22

2.2.7 DEVICE IDENTIFICATION AND REVISION............................................................................................................... 22

2.2.8 REGB REGISTER ....................................................................................................................................................... 23

2.2.9 MULTI-PURPOSE INPUTS AND OUTPUTS .............................................................................................................. 23

2.2.10 MPIO REGISTER ...................................................................................................................................................... 23

FIGURE 8. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT........................................................................................................... 24

3.0 CRYSTAL OSCILLATOR / BUFFER ................................................................................................... 26

FIGURE 9. TYPICAL OSCILLATOR CONNECTIONS............................................................................................................................... 26

FIGURE 10. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE........................................................................................ 26

4.0 TRANSMIT AND RECEIVE DATA ...................................................................................................... 27

4.1 FIFO DATA LOADING AND UNLOADING THROUGH THE DEVICE CONFIGURATION REGISTERS IN 32-BIT

FORMAT. ....................................................................................................................................................... 27

4.1.1 NORMAL RX FIFO DATA UNLOADING AT LOCATIONS 0X100, 0X300, 0X500, 0X700....................................... 27

4.1.2 SPECIAL RX FIFO DATA UNLOADING AT LOCATIONS 0X180, 0X380, 0X580, AND 0X780 .............................. 28

4.1.3 TX FIFO DATA LOADING AT LOCATIONS 0X100, 0X300, 0X500, 0X700, 0X900, 0XB00, 0XD00, 0XF00 .......... 28

4.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN

8-BIT FORMAT. ............................................................................................................................................. 29

TABLE 9: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE ............................................................ 29

5.0 UART .................................................................................................................................................... 30

5.1 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................... 30

FIGURE 11. BAUD RATE GENERATOR ............................................................................................................................................. 30

TABLE 10: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING........................................ 31

5.2 TRANSMITTER ............................................................................................................................................... 31

5.2.1 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY......................................................................................... 31

5.2.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. 31

FIGURE 12. TRANSMITTER OPERATION IN NON-FIFO MODE ............................................................................................................ 32

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
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