
xr
XR17D158
REV. 1.2.2
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
63
FIGURE 21. DEVICE CONFIGURATION AND UART REGISTERS READ OPERATION FOR A BYTE OR DWORD
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
TRDY#
IRDY#
DEVSEL#
1
23
4
Address
Bus
CMD
Byte Enable# = BYTE
BYTE
TRANSFE
R
PCI_RD1
5
6
7
PAR
PERR#
8
Note: PERR# and SERR are optional in a bus target application.
Even Parity is on AD[31:0], C/BE[3:0]#, and PAR
Data
Parity
Active
Host
Target
Host
Target
Data
BYTE
WA
IT
WA
IT
WAIT
Address
Parity
SERR#
Target
Targe
t
Active
Data
WORD
Byte Enable# = DWORD
DWORD
TRANSFE
R
WA
IT
WA
IT
Data
Parity
Active
910
11