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參數(shù)資料
| 型號： | XR16V794IV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 4/53頁 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 64B QUAD 64LQFP |
| 標準包裝： | 160 |
| 特點： | * |
| 通道數(shù)： | 4，QUART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 2.25 V ~ 3.6 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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XR16V794
12
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
REV. 1.0.1
NOTE: Table-B selected as Trigger Table for
2.9
THR and RHR Register Locations
The THR and RHR register addresses for channel 0 to channel 7 are shown in Table 5 below. The THR and
RHR for channels 0 to 7 are located at address 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60 and 0x70
respectively. Transmit data byte is loaded to the THR when writing to that address and receive data is
unloaded from the RHR register when reading that address. Both THR and RHR registers are 16C550
compatible in 8-bit format, so each bus operation can only write or read in bytes..
FIGURE 8. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
TABLE 5: TRANSMIT AND RECEIVE HOLDING REGISTER LOCATIONS, 16C550 COMPATIBLE
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X Clock
E
rror
T
a
gs
(64-
s
e
ts)
Er
ro
rTa
gs
i
n
LSR
bi
ts
4
:2
64 bytes by 11-bit
wide
FIFO
Receive Data Characters
FIFO Trigger=16
Example:
- RX FIFO trigger level selected at 16 bytes
(See Note Below)
Data fills to 24
Data falls to 8
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
THR and RHR Address Locations For CH0 to CH3 (16C550 Compatible)
CH0 0x00 Write THR
CH0 0x00 Read RHR
CH1 0x10 Write THR
CH1 0x10 Read RHR
CH2 0x20 Write THR
CH2 0x20 Read RHR
CH3 0x30 Write THR
CH3 0x30 Read RHR
784THRRHR1
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
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