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參數(shù)資料
| 型號： | XR16V794IV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 35/53頁 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 64B QUAD 64LQFP |
| 標準包裝： | 160 |
| 特點： | * |
| 通道數(shù)： | 4，QUART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 2.25 V ~ 3.6 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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XR16V794
40
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
REV. 1.0.1
EFR[5]: Special Character Detect Enable
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit for the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]=10) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]=01) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables the enhanced functions in IER bits 7:5, ISR bits 5:4, FCR bits
5:4, MCR bits 7:5, 3:2 and MSR 7:2 bits to be modified. After modifying any enhanced bits, EFR bit-4 can be
set to a logic 0 to latch the new values. This feature prevents legacy software from altering or overwriting the
enhanced functions once set. Normally, it is recommended to leave it enabled, logic 1.
Logic 0 = modification disable/latch enhanced features. IER bits 7:5, ISR bits 5:4, FCR bits 5:4, MCR bits 7:5,
3:2 and MSR 7:2 bits are saved to retain the user settings. After a reset, all these bits are set to a logic 0 to
be compatible with ST16C550 mode (default).
Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1 all enhanced features are
enabled.
EFR[3:0]: Software Flow Control Select
Combinations of software flow control can be selected by programming these bits, as shown in Table 18
below.
TABLE 18: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
EFR BIT-2
EFR BIT-1
EFR BIT-0
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0
No TX and RX flow control (default and reset)
0
X
No transmit flow control
1
0
X
Transmit Xon1, Xoff1
0
1
X
Transmit Xon2, Xoff2
1
X
Transmit Xon1 and Xon2, Xoff1 and Xoff2
X
0
No receive flow control
X
1
0
Receiver compares Xon1, Xoff1
X
0
1
Receiver compares Xon2, Xoff2
1
0
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
Transmit Xon1 and Xon2, Xoff1 and Xoff2
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
1
No transmit flow control
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
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