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參數(shù)資料
| 型號： | XR16L788IQ |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HIGH PERFORMANCE OCTAL UART |
| 中文描述： | 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 3 MM HEIGHT, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 26/42頁 |
| 文件大?。?/td> | 557K |
| 代理商： | XR16L788IQ |
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XR16L788 OCTAL UART
REV. 1.1.4
26
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in con-
junction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The
parity bit is a simple way used in communications for
data integrity check. See
Table 11
for parity selection
summary below.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the trans-
mission while the receiver checks for parity error of
the data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same for-
mat. (default).
Logic 1 = EVEN Parity is generated by forcing an
even the number of logic 1’s in the transmitted
character. The receiver must be programmed to
check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
LCR BIT-5 = logic 0, parity is not forced. (default)
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity
bit is forced to a logical 1 for the transmit and
receive data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity
bit is forced to a logical 0 for the transmit and
receive data.
T
ABLE
11: P
ARITY
SELECTION
LCR[6]: Transmit Break Enable
When enabled the Break control bit it causes a
break condition to be transmitted (the TX output is
forced to a “space’, logic 0, state). This condition
remains until disabled by setting LCR bit-6 to a
logic 0.
Logic 0 = No TX break condition. (default)
Logic 1 = Forces the transmitter output (TX) to a
“space”, logic 0, for alerting the remote receiver of a
line break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
Logic 0 = Data registers are selected. (default)
Logic 1 = Divisor latch registers are selected.
Modem Control Register (MCR) or General Pur-
pose Outputs Control.
This register controls the serial interface signals with
the modem or a peripheral device.
Modem Control Register (MCR)
The MCR register is used for controlling the modem
interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Pins
The DTR# pin may be used for automatic hardware
flow control enabled by EFR bit-6 and MCR bit-2=1. If
the modem interface is not used, this output may be
used for general purpose.
Logic 0 = Force DTR# output to a logic 1. (default)
Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Pins
The RTS# pin may be used for automatic hardware
flow control by enabled by EFR bit-6 and MCR bit-
2=0. If the modem interface is not used, this output
may be used for general purpose.
Logic 0 = Force RTS# output to a logic 1. (default)
Logic 1 = Force RTS# output to a logic 0.
MCR[2]: RTS/CTS or DTR/DSR for Auto Flow Con-
trol
DTR# or RTS# auto hardware flow control select.
This bit is in effect only when auto RTS/DTR is en-
abled by EFR bit-6.
Logic 0 = RTS# (RX side) and CTS# (TX side) pins
are used for auto hardware flow control.
Logic 1 = DTR# (RX side) and DSR# (TX side) pins
are used for auto hardware flow control.
MCR[3]:
Reserved. Logic zero is default.
BIT-2
W
ORD
LENGTH
S
TOP
BIT
LENGTH
(B
IT
TIME
(
S
))
0
1
1
5,6,7,8
5
6,7,8
1 (default)
1-1/2
2
LCR B
IT
-5 LCR B
IT
-4 LCR B
IT
-3
P
ARITY
SELECTION
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
No parity
Odd parity
Even parity
Force parity to mark, “1”
Forced parity to space,
“0”
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