參數(shù)資料
型號(hào)： XR16L788IQ
廠(chǎng)商： EXAR CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： HIGH PERFORMANCE OCTAL UART
中文描述： 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP100
封裝： 14 X 20 MM, 3 MM HEIGHT, PLASTIC, QFP-100
文件頁(yè)數(shù)： 14/42頁(yè)
文件大小： 557K
代理商： XR16L788IQ
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XR16L788 OCTAL UART
REV. 1.1.4
14
Programming the Baud Rate Generator Registers
DLM and DLL provides the capability of selecting the
operating data rate.
Table 6
shows the standard data
rates available with a 14.7456 MHz crystal or external
clock at 16X clock rate. At 8X sampling rate, these
data rates would double. When using a non-standard
data rate crystal or external clock, the divisor value
can be calculated for channel ‘N’ with the following
equation(s).
4.2
A
UTOMATIC
RTS/DTR H
ARDWARE
F
LOW
C
ON
-
TROL
O
PERATION
Automatic RTS/DTR flow control is used to prevent
data overrun to the local receiver FIFO. The RTS#/
DTR# output pin is used to request remote unit to
suspend/resume data transmission. The flow control
features are individually selected to fit specific appli-
cation requirement (see Figure 8):
- Select RTS (and CTS) or DTR (and DSR) through
MCR bit-2.
- Enable auto RTS/DTR flow control using EFR bit-6.
- The auto RTS/DTR function must be started by as-
serting RTS/DTR# output pin (MCR bit-0 or 1 to
logic 1 after it is enabled.
F
IGURE
7. B
AUD
R
ATE
G
ENERATOR
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL and DLM
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X or 8X
Sampling
Rate Clock to
Transmitter
and Receiver
To Other
Channels
Baud Rate
Generator
Logic
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16),
WHEN
8XMODE-
BIT
N
IS
0
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8),
WHEN
8XMODE-
BIT
N
IS
1
T
ABLE
6: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
AT
16X S
AMPLING
O
UTPUT
Data Rate
MCR Bit-7=1
O
UTPUT
Data Rate
MCR Bit-7=0
D
IVISOR
FOR
16x
Clock (Decimal)
D
IVISOR
FOR
16x
Clock (HEX)
DLM P
ROGRAM
V
ALUE
(HEX)
DLL P
ROGRAM
V
ALUE
(HEX)
D
ATA
R
ATE
E
RROR
(%)
100
600
1200
2400
4800
9600
19.2k
38.4k
57.6k
115.2k
230.4k
400
2400
4800
9600
19.2k
38.4k
76.8k
153.6k
230.4k
460.8k
921.6k
2304
384
192
96
48
24
12
6
4
2
1
900
180
C0
60
30
18
0C
06
04
02
01
09
01
00
00
00
00
00
00
00
00
00
00
80
C0
60
30
18
0C
06
04
02
01
0
0
0
0
0
0
0
0
0
0
0
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