參數(shù)資料
型號： XR16L788IQ
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： HIGH PERFORMANCE OCTAL UART
中文描述： 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP100
封裝： 14 X 20 MM, 3 MM HEIGHT, PLASTIC, QFP-100
文件頁數(shù)： 25/42頁
文件大?。?/td> 557K
代理商： XR16L788IQ
XR16L788 OCTAL UART
á
REV. 1.1.4
25
Logic 1 = Reset the transmit FIFO pointers and FIFO
level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after
resetting the FIFO.
FCR[3]: DMA Mode Select
This bit has no effect since TXRDY and RXRDY pins
are not available in this device. It is provided for lega-
cy software.
Logic 0 = Set DMA to mode 0. (default)
Logic 1 = Set DMA to mode 1.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
The FCTR Bits 6-7 are associated with these 2 bits by
selecting one of the four tables. The 4 user selectable
trigger levels in 4 tables are supported for compatibili-
ty reasons. These 2 bits set the trigger level for the
transmit FIFO interrupt. The UART will issue a trans-
mit interrupt when the number of characters in the
FIFO falls below the selected trigger level, or when it
gets empty in case that the FIFO did not get filled
over the trigger level on last re-load.
Table 10
below
shows the selections.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 6-7 are associated with these 2 bits.
These 2 bits are used to set the trigger level for the
receiver FIFO interrupt.
Table 10
shows the complete
selections.
Line Control Register (LCR)
The Line Control Register is used to specify the asyn-
chronous data communication format. The word or
character length, the number of stop bits, and the par-
ity are selected by writing the appropriate bits in this
register.
LCR[1-0]: TX and RX Word Length Select
These two bits specify the word length to be transmit-
ted or received.
T
ABLE
10: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
FCTR
B
IT
-7
FCTR
B
IT
-6
FCR
B
IT
-7
FCR
B
IT
-6
FCR
B
IT
-5
FCR
BIT
-4
R
ECEIVE
T
RIGGER
L
EVEL
T
RANSMIT
T
RIGGER
L
EVEL
C
OMPATIBILITY
0
0
0
0
1
1
0
1
0
1
0
0
1 (default)
4
8
14
1 (default)
Table-A. 16C550, 16C2550,
16C2552, 16C554, 16C580
compatible.
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
8
16
24
28
16
8
24
30
Table-B. 16C650A compatible.
1
0
0
0
1
1
X
0
1
0
1
X
0
0
1
1
0
1
0
1
8
16
56
60
8
16
32
56
Table-C. 16C654 compatible.
1
1
X
X
Programmable Programmable Table-D. 16C850, 16c2850,
16C2852, 16C854, 16C864,
16C872 compatible.
BIT-1
BIT-0
W
ORD
LENGTH
0
0
1
1
0
1
0
1
5 (default)
6
7
8
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