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XR16C864
16
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
REV. 2.2.0
NOTE: Table-B selected as Trigger Table for
Figure 9 (Table 11).
2.14
Auto RTS Hardware Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 10):
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE
FIGURE 9. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
Receive Data Shift
Register (RSR)
RXFIFO1
16X Clock
E
rr
o
r
T
a
g
s
(1
2
8
-s
e
ts
)
E
rr
o
r
T
a
g
s
in
L
S
R
b
it
s
4
:2
128 bytes by 11-bit
wide
FIFO
Receive Data Characters
FIFO
Trigger=16
Example
:
- RX FIFO trigger level selected at 16
bytes
(See Note Below)
Data fills to
24
Data falls to
8
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.