NOTE: TR = Tape and Re" />
參數(shù)資料
型號: XR16C864IQ-F
廠商: Exar Corporation
文件頁數(shù): 23/51頁
文件大小: 0K
描述: IC UART FIFO 128B QUAD 100QFP
標(biāo)準(zhǔn)包裝: 66
特點(diǎn): *
通道數(shù): 4,QUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 100-BQFP
供應(yīng)商設(shè)備封裝: 100-QFP(14x20)
包裝: 托盤
其它名稱: 1016-1277
XR16C864
3
REV. 2.2.0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
NOTE: TR = Tape and Reel, -F = Green / RoHS
PIN DESCRIPTIONS
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
DEVICE STATUS
XR16C864CQ-F
100-Lead QFP
0°C to +70°C
Active
XR16C864CQTR-F
100-Lead QFP
0°C to +70°C
Active
XR16C864IQ-F
100-Lead QFP
-40°C to +85°C
Active
XR16C864IQTR-F
100-Lead QFP
-40°C to +85°C
Active
Pin Description
NAME
100-QFP
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
37
38
39
I
Address data lines [2:0]. These 3 address lines select one of the internal registers in
UART channels A-D during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
95
94
93
92
91
90
89
88
I/O
Data bus lines [7:0] (bidirectional).
IOR#
(N.C.)
66
I
When 16/68# pin is at logic 1, the Intel bus interface is selected and this input becomes
read strobe (active low). The falling edge instigates an internal read cycle and retrieves
the data byte from an internal register pointed by the address lines [A2:A0], puts the data
byte on the data bus to allow the host processor to read it on the rising edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input is not
used.
IOW#
(R/W#)
15
I
When 16/68# pin is at logic 1, it selects Intel bus interface and this input becomes write
strobe (active low). The falling edge instigates the internal write cycle and the rising edge
transfers the data byte on the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input
becomes read (logic 1) and write (logic 0) signal.
CSA#
(CS#)
13
I
When 16/68# pin is at logic 1, this input is chip select A (active low) to enable channel A in
the device.
When 16/68# pin is at logic 0, this input becomes the chip select (active low) for the
Motorola bus interface.
CSB#
(A3)
17
I
When 16/68# pin is at logic 1, this input is chip select B (active low) to enable channel B in
the device.
When 16/68# pin is at logic 0, this input becomes address line A3 which is used for chan-
nel selection in the Motorola bus interface.
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