參數(shù)資料
型號(hào): XQ2V6000
廠商: Xilinx, Inc.
英文描述: QPro Virtex-II 1.5V Military QML Platform FPGAs
中文描述: QPro的Virtex - II 1.5V的軍事QML第平臺(tái)FPGA
文件頁(yè)數(shù): 29/128頁(yè)
文件大?。?/td> 2738K
代理商: XQ2V6000
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QPro Virtex-II 1.5V Military QML Platform FPGAs
DS122 (v1.1) January 7, 2004
Product Specification
www.xilinx.com
1-800-255-7778
29
R
A write operation performs a simultaneous read operation.
Three different options are available, selected by configura-
tion:
1.
“WRITE_FIRST”
The “WRITE_FIRST” option is a transparent mode. The
same clock edge that writes the data input (DI) into the
memory also transfers DI into the output registers DO
as shown in
Figure 32
.
2.
“READ_FIRST”
The “READ_FIRST” option is a read-before-write mode.
The same clock edge that writes data input (DI) into the
memory also transfers the prior content of the memory
cell addressed into the data output registers DO, as
shown in
Figure 33
.
3.
“NO_CHANGE”
The “NO_CHANGE” option maintains the content of the
output registers, regardless of the write operation. The
clock edge during the write mode has no effect on the
content of the data output register DO. When the port is
configured as “NO_CHANGE”, only a read operation
loads a new value in the output register DO, as shown in
Figure 34
.
Figure 32:
WRITE_FIRST Mode
CLK
WE
Data_in
Data_in
New
aa
Address
Internal
Memory
DO
Data_out = Data_in
Data_out
DI
DS031_14_102000
New
RAM Contents
New
Old
Figure 33:
READ_FIRST Mode
CLK
WE
Data_in
Data_in
New
aa
Old
Address
Internal
Memory
DO
Prior stored data
Data_out
DI
DS031_13_102000
RAM Contents
New
Old
ds122_1_1.fm Page 29 Wednesday, January 7, 2004 9:15 PM
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