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參數(shù)資料
| 型號(hào)： | XQ18V04VQ44N |
| 廠商： | XILINX INC |
| 元件分類： | DRAM |
| 英文描述： | QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs |
| 中文描述： | 512K X 8 CONFIGURATION MEMORY, PQFP44 |
| 封裝： | PLASTIC, VQFP-44 |
| 文件頁(yè)數(shù)： | 1/18頁(yè) |
| 文件大?。?/td> | 163K |
| 代理商： | XQ18V04VQ44N |
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DS082 (v1.2) November 5, 2001
Preliminary Product Specification
1-800-255-77781
2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
In-system programmable 3.3V PROMs for
configuration of Xilinx FPGAs
-
Endurance of 2,000 program/erase cycles
-
Program/erase over full military temperature range
IEEE Std 1149.1 boundary-scan (JTAG) support
Cascadable for storing longer or multiple bitstreams
Dual configuration modes
-
Serial Slow/Fast configuration (up to 33 MHz)
-
Parallel (up to 264 Mbps at 33 MHz)
Low-power advanced CMOS FLASH process
5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals.
3.3V or 2.5V output capability
Available in CC44 and VQ44 packages.
Design support using the Xilinx Alliance and
Foundation series software packages.
JTAG command initiation of standard FPGA
configuration.
Available to Standard Microcircuit Drawing
5962-01525.
-
For more information contact Defense Supply
Center Columbus (DSCC) at
http://www.dscc.dla.mil
Radiation Hardenned XQR18V04
Fabricated on Epitaxial Substrate
Latch-Up Immune to >120 LET
Guaranteed TID of 40 kRad(Si)
Supports SEU Scrubbing
Description
Xilinx introduces the QPro XQ18V04 and XQR18V04
series of QML in-system programmable and radiation hard-
ened configuration PROMs. Initial devices in this 3.3V fam-
ily are a 4-megabit PROM that provide an easy-to-use,
cost-effective method for re-programming and storing large
Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising CCLK, data is available on the PROM
DATA (D0) pin that is connected to the FPGA D
IN
pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. When the FPGA is in Slave
Serial mode, the PROM and the FPGA are clocked by an
external clock.
When the FPGA is in Express or SelectMAP Mode, an
external oscillator will generate the configuration clock that
drives the PROM and the FPGA. After the rising CCLK
edge, data are available on the PROMs DATA (D0-D7) pins.
The data will be clocked into the FPGA on the following ris-
ing edge of the CCLK. Neither Express nor SelectMAP uti-
lize a Length Count, so a free-running oscillator may be
used. See
Figure 6
.
0
QPro XQ18V04 (XQR18V04) QML
In-System Programmable
Configuration PROMs
Preliminary Product Specification
DS082 (v1.2) November 5, 2001
0
5
R
Figure 1:
XQ18V04 Series Block Diagram
Control
and
JTAG
Interface
Memory
Serial
or
Parallel
Interface
D0 DATA
(Serial or Parallel
[Express/SelectMAP] Mode)
D[1:7]
Express Mode and
SelectMAP Interface
Data
Address
CLK CE
TCK
TMS
TDI
TDO
OE/Reset
CEO
Data
DS026_01_021000
7
CF
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