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QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
DS082 (v1.2) November 5, 2001
Preliminary Product Specification
1-800-255-7778 R 5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tol-
erant even through the core power supply is 3.3V. This
allows 5V CMOS signals to connect directly to the PROM
inputs without damage. In addition, the 3.3V V
CC
power
supply can be applied before or after 5V signals are applied
to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,
the core power supply (V
CC
), and the output power supply
(V
CCO
) may have power applied in any order. This makes
the PROM devices immune to power supply sequencing
issues.
Reset Activation
On power up, OE/RESET is held low until the XQ(R)18V04
is active (1 ms) and able to supply data after receiving a
CCLK pulse from the FPGA. OE/RESET is connected to an
external resistor to pull OE/RESET HIGH releasing the
FPGA INIT and allowing configuration to begin. OE/RESET
is held low until the XQ(R)18V04 voltage reaches the oper-
ating voltage range. If the power drops below 2.0V, the
PROM will reset. OE/RESET polarity is NOT programma-
ble.
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high-impedance
state regardless of the state of the OE input. JTAG pins
TMS, TDI and TDO can be in a high-impedance state or
High.
Customer Control Pins
The XQ(R)18V04 PROMs have various control bits accessi-
ble by the customer. These can be set after the array has
been programmed using "Skip User Array" in Xilinx JTAG
Programmer Software.
Table 6:
Truth Table for PROM Control Inputs
Control Inputs
Internal Address
Outputs
OE/RESET
CE
DATA
CEO
I
CC
High
Low
If address < TC
(1)
: increment
If address > TC
(1)
: don
’
t change
Active
High-Z
High
Low
Active
Reduced
Low
Low
Held reset
High-Z
High
Active
High
High
Held reset
High-Z
High
Standby
Low
High
Held reset
High-Z
High
Standby
Notes:
1.
TC = Terminal Count = highest address value. TC + 1 = address 0.