參數(shù)資料
型號(hào)： XC6VCX240T-2FFG784I
廠(chǎng)商： Xilinx Inc
文件頁(yè)數(shù)： 31/52頁(yè)
文件大?。?/td> 0K
描述： IC FPGA VIRTEX 6 241K 784FFGBGA
產(chǎn)品培訓(xùn)模塊： Virtex-6 FPGA Overview
產(chǎn)品變化通告： Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝： 1
系列： Virtex® 6 CXT
LAB/CLB數(shù)： 18840
邏輯元件/單元數(shù)： 241152
RAM 位總計(jì)： 15335424
輸入/輸出數(shù)： 400
電源電壓： 0.95 V ~ 1.05 V
安裝類(lèi)型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 784-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 784-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
37
Block RAM and FIFO Switching Characteristics
Table 50: Block RAM and FIFO Switching Characteristics
Symbol
Description
Speed Grade
Units
-2
-1
Block RAM and FIFO Clock-to-Out Delays
TRCKO_DO and TRCKO_DO_REG(1) Clock CLK to DOUT output (without output register)(2)(3)
2.08
2.39
ns, Max
Clock CLK to DOUT output (with output register)(4)(5)
0.75
0.86
ns, Max
TRCKO_DO_ECC and
TRCKO_DO_ECC_REG
Clock CLK to DOUT output with ECC
(without output register)(2)(3)
3.30
3.79
ns, Max
Clock CLK to DOUT output with ECC (with output register)(4)(5)
0.86
0.98
ns, Max
TRCKO_CASC and
TRCKO_CASC_REG
Clock CLK to DOUT output with Cascade
(without output register)(2)
3.18
3.65
ns, Max
Clock CLK to DOUT output with Cascade (with output register)(4)
1.58
1.81
ns, Max
TRCKO_FLAGS
Clock CLK to FIFO flags outputs(6)
0.91
1.05
ns, Max
TRCKO_POINTERS
Clock CLK to FIFO pointers outputs(7)
1.09
1.25
ns, Max
TRCKO_RDCOUNT
Clock CLK to FIFO Read Counter
1.09
1.25
ns, Max
TRCKO_WRCOUNT
Clock CLK to FIFO Write Counter
1.09
1.25
ns, Max
TRCKO_SDBIT_ECC and
TRCKO_SDBIT_ECC_REG
Clock CLK to BITERR (with output register)
0.76
0.87
ns, Max
Clock CLK to BITERR (without output register)
2.84
3.26
ns, Max
TRCKO_PARITY_ECC
Clock CLK to ECCPARITY in ECC encode only mode
1.06
1.21
ns, Max
TRCKO_RDADDR_ECC and
TRCKO_RDADDR_ECC_REG
Clock CLK to RDADDR output with ECC (without output register)
0.90
1.03
ns, Max
Clock CLK to RDADDR output with ECC (with output register)
0.92
1.06
ns, Max
Setup and Hold Times Before/After Clock CLK
TRCCK_ADDR/TRCKC_ADDR
ADDR inputs(8)
0.62/0.32
0.72/0.37
ns, Min
TRDCK_DI/TRCKD_DI
DIN inputs(9)
1.11/0.34
1.28/0.39
ns, Min
TRDCK_DI_ECC/TRCKD_DI_ECC
DIN inputs with block RAM ECC in standard mode(9)
0.59/0.34
0.68/0.39
ns, Min
DIN inputs with block RAM ECC encode only(9)
0.85/0.34
0.97/0.39
ns, Min
DIN inputs with FIFO ECC in standard mode(9)
1.02/0.34
1.17/0.39
ns, Min
TRCCK_CLK/TRCKC_CLK
Inject single/double bit error in ECC mode
1.20/0.29
1.38/0.33
ns, Min
TRCCK_RDEN/TRCKC_RDEN
Block RAM Enable (EN) input
0.41/0.30
0.47/0.34
ns, Min
TRCCK_REGCE/TRCKC_REGCE
CE input of output register
0.22/0.31
0.25/0.35
ns, Min
TRCCK_RSTREG/TRCKC_RSTREG
Synchronous RSTREG input
0.28/0.26
0.32/0.29
ns, Min
TRCCK_RSTRAM/TRCKC_RSTRAM
Synchronous RSTRAM input
0.41/0.27
0.47/0.31
ns, Min
TRCCK_WE/TRCKC_WE
Write Enable (WE) input (block RAM only)
0.52/0.35
0.60/0.40
ns, Min
TRCCK_WREN/TRCKC_WREN
WREN FIFO inputs
0.55/0.30
0.64/0.34
ns, Min
TRCCK_RDEN/TRCKC_RDEN
RDEN FIFO inputs
0.55/0.30
0.63/0.34
ns, Min
Reset Delays
TRCO_FLAGS
Reset RST to FIFO Flags/Pointers(10)
1.10
1.27
ns, Max
TRCCK_RSTREG/TRCKC_RSTREG
FIFO reset timing(11)
0.28/0.26
0.32/0.29
ns, Min
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參數(shù)描述
XC6VCX75T 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-6 CXT Family Data Sheet
XC6VCX75T-1FF484C 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 74496 CELLS 40NM (CMOS) TECHNOLOGY - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 75K 484BGA
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