參數(shù)資料
型號: XC3S700AN-4FG484I
廠商: Xilinx Inc
文件頁數(shù): 84/123頁
文件大小: 0K
描述: IC FPGA SPARTAN 3AN 484FBGA
標(biāo)準包裝: 60
系列: Spartan®-3AN
LAB/CLB數(shù): 1472
邏輯元件/單元數(shù): 13248
RAM 位總計: 368640
輸入/輸出數(shù): 372
門數(shù): 700000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-BBGA
供應(yīng)商設(shè)備封裝: 484-FBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
63
Master Serial and Slave Serial Mode Timing
Table 54: Slave Mode CCLK Input Low and High Time
Symbol
Description
Min
Max
Units
TSCCL,
TSCCH
CCLK Low and High time
5
ns
X-Ref Target - Figure 14
Figure 14: Waveforms for Master Serial and Slave Serial Configuration
Table 55: Timing for the Master Serial and Slave Serial Configuration Modes
Symbol
Description
Slave/
Master
All Speed Grades
Units
Min
Max
Clock-to-Output Times
TCCO
The time from the falling transition on the CCLK pin to data appearing at the
DOUT pin
Both
1.5
10
ns
Setup Times
TDCC
The time from the setup of data at the DIN pin to the rising transition at the
CCLK pin
Both
7
–ns
Hold Times
TCCD
The time from the rising transition at the CCLK pin to the point when data is
last held at the DIN pin
Master
0
ns
Slave
1.0
Clock Timing
TCCH
High pulse width at the CCLK input pin
Master
Slave
TCCL
Low pulse width at the CCLK input pin
Master
Slave
FCCSER
Frequency of the clock signal at the
CCLK input pin(2)
No bitstream compression
Slave
0
100
MHz
With bitstream compression
0
100
MHz
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 10.
2.
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
DS312-3_05_103105
Bit 0
Bit 1
Bit n
Bit n+1
Bit n-64
Bit n-63
1/F
CCSER
T
SCCL
T
DCC
T
CCD
T
SCCH
T
CCO
PROG_B
(Input)
DIN
(Input)
DOUT
(Output)
(Open-Drain)
INIT_B
(Input/Output)
CCLK
T
MCCL
T
MCCH
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