參數(shù)資料
型號： XC3S700AN-4FG484I
廠商： Xilinx Inc
文件頁數(shù)： 74/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 3AN 484FBGA
標準包裝： 60
系列： Spartan®-3AN
LAB/CLB數(shù)： 1472
邏輯元件/單元數(shù)： 13248
RAM 位總計： 368640
輸入/輸出數(shù)： 372
門數(shù)： 700000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
54
Digital Frequency Synthesizer (DFS)
Delay Lines
DCM_DELAY_STEP(5)
Finest delay resolution, average over all taps
All
15
35
15
35
ps
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 10 and Table 39.
2.
Indicates the maximum amount of output jitter that th
e DCM adds to the jitter on the CLKIN input.
3.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter
of “±[1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns
or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250 ps.
5.
The typical delay step size is 23 ps.
Table 41: Recommended Operating Conditions for the DFS
Symbol
Description
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Input Frequency Ranges(2)
FCLKIN
CLKIN_FREQ_FX
Frequency for the CLKIN input
0.200
0.200
MHz
Input Clock Jitter Tolerance(4)
CLKIN_CYC_JITT_FX_LF
Cycle-to-cycle jitter at the
CLKIN input, based on CLKFX
output frequency
FCLKFX < 150 MHz
–±300
ps
CLKIN_CYC_JITT_FX_HF
FCLKFX > 150 MHz
–±150
ps
CLKIN_PER_JITT_FX
Period jitter at the CLKIN input
–±1
ns
Notes:
1.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
2.
If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 39.
3.
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.
4.
CLKIN input jitter beyond these limits may cause the DCM to lose lock.
Table 40: Switching Characteristics for the DLL (Cont’d)
Symbol
Description
Device
Speed Grade
Units
-5
-4
Min
Max
Min
Max
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3S700AN-4FGG484C 功能描述:IC SPARTAN-3AN FPGA 700K 484FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3AN 標準包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241
XC3S700AN-4FGG484CES 制造商:Xilinx 功能描述:
XC3S700AN-4FGG484I 功能描述:IC FPGA SPARTAN -3AN700K 484FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3AN 標準包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計:226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28）
XC3S700AN-5FG484C 制造商:Xilinx 功能描述:FPGA SPARTAN-3AN FAMILY 700K GATES 13248 CELLS 770MHZ 90NM T - Trays 制造商:Xilinx 功能描述:IC FPGA 372 I/O 484FBGA
XC3S700AN-5FGG484C 功能描述:IC FPGA SPARTAN-3A 700K 484-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3AN 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
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