參數(shù)資料
型號: XC3S400AN-4FTG256C
廠商: Xilinx Inc
文件頁數(shù): 77/123頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-3AN
LAB/CLB數(shù): 896
邏輯元件/單元數(shù): 8064
RAM 位總計(jì): 368640
輸入/輸出數(shù): 195
門數(shù): 400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
57
DNA Port Timing
Internal SPI Access Port Timing
Table 46: DNA_PORT Interface Timing
Symbol
Description
Min
Max
Units
TDNASSU
Setup time on SHIFT before the rising edge of CLK
1.0
–ns
TDNASH
Hold time on SHIFT after the rising edge of CLK
0.5
–ns
TDNADSU
Setup time on DIN before the rising edge of CLK
1.0
–ns
TDNADH
Hold time on DIN after the rising edge of CLK
0.5
–ns
TDNARSU
Setup time on READ before the rising edge of CLK
5.0
10,000
ns
TDNARH
Hold time on READ after the rising edge of CLK
0
–ns
TDNADCKO
Clock-to-output delay on DOUT after rising edge of CLK
0.5
1.5
ns
TDNACLKF
CLK frequency
0
100
MHz
TDNACLKH
CLK High time
1.0
ns
TDNACLKL
CLK Low time
1.0
ns
Notes:
1.
The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10 s.
Table 47: SPI_ACCESS Interface Timing
Symbol
Description
Speed Grade
Units
-5
-4
Min
Max
Min
Max
TSPICCK_MOSI
Setup time on MOSI before the active edge of CLK
4.47
–5.0
–ns
TSPICKC_MOSI
Hold time on MOSI after the active edge of CLK
4.03
–4.5
–ns
TCSB
CSB High time
50
–50
–ns
TSPICCK_CSB
Setup time on CSB before the active edge of CLK
7.15
–8.0
–ns
TSPICCK_CSB
Hold time on CSB after the active edge of CLK
7.15
–8.0
–ns
TSPICKO_MISO
Clock-to-output delay on MISO after active edge of CLK
–14.3
16.0
ns
FSPICLK
CLK frequency
–50
MHz
FSPICAR1
CLK frequency for Continuous Array Read command
–50
MHz
FSPICAR1
CLK frequency for Continuous Array Read command,
reduced initial latency
–33
MHz
TSPICLKL
CLK High time
ns
TSPICLKH
CLK Low time
6.8
6.8
ns
Notes:
1.
For details on using SPI_ACCESS and the In-System Flash memory, see UG333 Spartan-3AN FPGA In-System Flash User Guide.
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