參數(shù)資料
型號： XC3S400AN-4FTG256C
廠商： Xilinx Inc
文件頁數(shù)： 32/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3AN
LAB/CLB數(shù)： 896
邏輯元件/單元數(shù)： 8064
RAM 位總計： 368640
輸入/輸出數(shù)： 195
門數(shù)： 400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
16
Quiescent Current Requirements
Table 12: Spartan-3AN FPGA Quiescent Supply Current Characteristics
Symbol
Description
Device
Commercial
Maximum(2)
Industrial
Maximum(2)
Units
ICCINTQ
Quiescent VCCINT supply current
XC3S50AN
2
20
30
mA
XC3S200AN
7
50
70
mA
XC3S400AN
10
85
125
mA
XC3S700AN
13
120
185
mA
XC3S1400AN
24
220
310
mA
ICCOQ
Quiescent VCCO supply current
XC3S50AN
0.2
2
3
mA
XC3S200AN
0.2
2
3
mA
XC3S400AN
0.3
3
4
mA
XC3S700AN
0.3
3
4
mA
XC3S1400AN
0.3
3
4
mA
ICCAUXQ
Quiescent VCCAUX supply current
XC3S50AN
3.1
8.1
10.1
mA
XC3S200AN
5.1
12.1
15.1
mA
XC3S400AN
5.1
18.1
24.1
mA
XC3S700AN
6.1
28.1
34.1
mA
XC3S1400AN
10.1
50.1
58.1
mA
Notes:
1.
The numbers in this table are based on the conditions set forth in Table 10.
2.
Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads
disabled. The internal SPI Flash is deselected (CSB = High); the internal SPI Flash current is consumed on the VCCAUX supply rail. Typical
values are characterized using typical devices at room temperature (TJ of 25°C at VCCINT = 1.2V, VCCO = 3.3V, and VCCAUX = 3.3V). The
maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with
VCCINT = 1.26V, VCCO = 3.6V, and VCCAUX = 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, a design with no
functional elements instantiated). For conditions other than those described above (for example, a design including functional elements),
measured quiescent current levels will be different than the values in the table.
3.
There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The
Spartan-3AN FPGA XPower Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design, and b)
XPower Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates. For more information on
power for the In-System Flash memory, see the Power Management chapter of UG333.
4.
The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
5.
For information on the power-saving Suspend mode, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs. Suspend mode
typically saves 40% total power consumption compared to quiescent current.
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