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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | XC3S400AN-4FTG256C |
| 寤犲晢锛� | Xilinx Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 52/123闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FPGA SPARTAN-3AN 256FTBGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | Spartan®-3AN |
| LAB/CLB鏁�(sh霉)锛� | 896 |
| 閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 8064 |
| RAM 浣嶇附瑷�(j矛)锛� | 368640 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 195 |
| 闁€鏁�(sh霉)锛� | 400000 |
| 闆绘簮闆诲锛� | 1.14 V ~ 1.26 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 85°C |
| 灏佽/澶栨锛� | 256-LBGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 256-FTBGA |
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Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
34
TIOPLID
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with the input
delay programmed
LVCMOS25(2)
1
XC3S1400AN
1.93
2.40
ns
2
2.69
3.15
ns
3
3.52
3.99
ns
4
3.89
4.55
ns
5
3.95
4.42
ns
6
4.53
5.32
ns
7
5.30
6.21
ns
8
5.83
6.80
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
2.
This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 26.
Table 25: Propagation Times for the IOB Input Path (Cont鈥檇)
Symbol
Description
Conditions
DELAY_VALUE
Device
Speed
Grade
Units
-5
-4
Max
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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| RSA50DTAD-S664 | CONN EDGECARD 100PS R/A .125 SLD |
| 24LC32AFT-E/OT | IC SRL EEPROM 4KX8 2.5V SOT23-5 |
| RMA50DTAD-S664 | CONN EDGECARD 100PS R/A .125 SLD |
| 24AA32AFT-I/MS | IC SRL EEPROM 4KX8 1.8V 8-MSOP |
| XC3S200A-4FG320I | IC SPARTAN-3A FPGA 200K 320FBGA |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
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| XC3S400AN-5FG400C | 鍒堕€犲晢:Xilinx 鍔熻兘鎻忚堪:FPGA SPARTAN-3AN FAMILY 400K GATES 8064 CELLS 770MHZ 90NM TE - Trays 鍒堕€犲晢:Xilinx 鍔熻兘鎻忚堪:IC FPGA SPARTAN-3AN 400K 400BGA 鍒堕€犲晢:Xilinx 鍔熻兘鎻忚堪:IC FPGA 311 I/O 400FBGA |
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| XC3S400AN-5FT256C | 鍒堕€犲晢:Xilinx 鍔熻兘鎻忚堪:SPARTAN3AN - Trays 鍒堕€犲晢:Xilinx 鍔熻兘鎻忚堪:IC FPGA 195 I/O 256FTBGA |
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