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參數(shù)資料
| 型號： | XC3S1200E-5FTG256C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 60/227頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN3E 1200K 256FTBGA |
| 標準包裝： | 90 |
| 系列： | Spartan®-3E |
| LAB/CLB數(shù)： | 2168 |
| 邏輯元件/單元數(shù)： | 19512 |
| RAM 位總計： | 516096 |
| 輸入/輸出數(shù)： | 190 |
| 門數(shù)： | 1200000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 256-LBGA |
| 供應商設(shè)備封裝： | 256-FTBGA |
Spartan-3E FPGA Family: DC and Switching Characteristics
DS312 (v4.1) July 19, 2013
Product Specification
152
Byte Peripheral Interface (BPI) Configuration Timing
X-Ref Target - Figure 77
Figure 77: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration (BPI-DN mode shown)
Table 120: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
Symbol
Description
Minimum
Maximum
Units
TCCLK1
Initial CCLK clock period
See Table 112
TCCLKn
CCLK clock period after FPGA loads ConfigRate setting
See Table 112
TMINIT
Setup time on CSI_B, RDWR_B, and M[2:0] mode pins before the rising edge of
INIT_B
50
-ns
TINITM
Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising edge of
INIT_B
0
-ns
TINITADDR
Minimum period of initial A[23:0] address cycle; LDC[2:0]
and HDC are asserted and valid
BPI-UP:
(M[2:0] = <0:1:0>)
55
TCCLK1
cycles
BPI-DN:
(M[2:0] = <0:1:1>)
22
TCCO
Address A[23:0] outputs valid after CCLK falling edge
See Table 116
TDCC
Setup time on D[7:0] data inputs before CCLK rising edge
See Table 116
TCCD
Hold time on D[7:0] data inputs after CCLK rising edge
See Table 116
(Input)
HSWAP must be stable before INIT_B goes High and constant throughout the configuration process.
Data
Address
Data
Address
Byte 0
000_0000
INIT_B
<0:1:0>
M[2:0]
T
MINIT
T
INITM
LDC[2:0]
HDC
CSO_B
Byte 1
000_0001
CCLK
A[23:0]
D[7:0]
T
DCC
T
CCD
T
AVQV
T
CCLK1
(Input)
T
INITADDR
T
CCLKn
T
CCLK1
T
CCO
HSWAP
New ConfigRate active
Pin initially pulled High by internal pull-up resistor if HSWAP input is Low.
Pin initially high-impedance (Hi-Z) if HSWAP input is High.
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
(Input)
PROG_B
(Input)
DS312-3_08_032409
(Open-Drain)
Shaded values indicate specifications on attached parallel NOR Flash PROM.
Address
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|---|---|
| XC3S1200E-5FTG256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
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