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參數(shù)資料
| 型號(hào)： | XC3S1200E-4FTG256I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 205/227頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN3E 1200K 256FTBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan®-3E |
| LAB/CLB數(shù)： | 2168 |
| 邏輯元件/單元數(shù)： | 19512 |
| RAM 位總計(jì)： | 516096 |
| 輸入/輸出數(shù)： | 190 |
| 門數(shù)： | 1200000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
79
VS[2:0]
Input
Variant Select. Instructs the FPGA how
to communicate with the attached SPI
Flash PROM. See Design Considerations
Must be at the logic levels shown
in Table 53. Sampled when
INIT_B goes High.
User I/O
MOSI
Output
Serial Data Output.
FPGA sends SPI Flash memory
read commands and starting
address to the PROM’s serial
data input.
User I/O
DIN
Input
Serial Data Input.
FPGA receives serial data from
PROM’s serial data output.
User I/O
CSO_B
Output
Chip Select Output. Active Low.
Connects to the SPI Flash
PROM’s chip-select input. If
HSWAP = 1, connect this signal
to a 4.7 k
Ω pull-up resistor to
3.3V.
Drive CSO_B High after
configuration to disable the
SPI Flash and reclaim the
MOSI, DIN, and CCLK pins.
Optionally, re-use this pin
and MOSI, DIN, and CCLK
to continue communicating
with SPI Flash.
CCLK
Output
Configuration Clock. Generated by
FPGA internal oscillator. Frequency
controlled by ConfigRate bitstream
generator option. If CCLK PCB trace is
long or has multiple connections,
terminate this output to maintain signal
integrity. See CCLK Design
Drives PROM’s clock input.
User I/O
DOUT
Output
Serial Data Output.
Actively drives. Not used in
single-FPGA designs. In a
daisy-chain configuration, this
pin connects to DIN input of the
next FPGA in the chain.
User I/O
INIT_B
Open-drain
bidirectional
I/O
Initialization Indicator. Active Low.
Goes Low at start of configuration during
Initialization memory clearing process.
Released at end of memory clearing,
when mode select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 k
Ω pull-up
resistor to VCCO_2.
Active during configuration. If
SPI Flash PROM requires
> 2 ms to awake after powering
on, hold INIT_B Low until PROM
is ready. If CRC error detected
during configuration, FPGA
drives INIT_B Low.
User I/O. If unused in the
application, drive INIT_B
High.
DONE
Open-drain
bidirectional
I/O
FPGA Configuration Done. Low during
configuration. Goes High when FPGA
successfully completes configuration.
Requires external 330
Ω pull-up resistor
to 2.5V.
Low indicates that the FPGA is
not yet configured.
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
PROG_B
Input
Program FPGA. Active Low. When
asserted Low for 500 ns or longer, forces
the FPGA to restart its configuration
process by clearing configuration
memory and resetting the DONE and
INIT_B pins once PROG_B returns High.
Recommend external 4.7 k
Ω pull-up
resistor to 2.5V. Internal pull-up value
may be weaker (see Table 78). If driving
externally with a 3.3V output, use an
open-drain or open-collector driver or use
a current limiting series resistor.
Must be High to allow
configuration to start.
Drive PROG_B Low and
release to reprogram FPGA.
Hold PROG_B to force
FPGA I/O pins into Hi-Z,
allowing direct programming
access to SPI Flash PROM
pins.
Table 55: Serial Peripheral Interface (SPI) Connections (Cont’d)
Pin Name
FPGA
Direction
Description
During Configuration
After Configuration
S
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| XC3S1200E-4PQ208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S1200E-4PQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S1200E-4PQG208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S1200E-4PQG208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S1200E-4TQ144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family |
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