參數(shù)資料
型號(hào): XC3042A-7PQ100C
廠商: Xilinx Inc
文件頁數(shù): 22/76頁
文件大?。?/td> 0K
描述: IC LOGIC CL ARRAY 4200GAT 100PQF
產(chǎn)品變化通告: Product Discontinuation 27/Apr/2010
標(biāo)準(zhǔn)包裝: 1
系列: XC3000A/L
LAB/CLB數(shù): 144
RAM 位總計(jì): 30784
輸入/輸出數(shù): 82
門數(shù): 3000
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 100-BQFP
供應(yīng)商設(shè)備封裝: 100-QFP(14x20)
其它名稱: 122-1026
R
November 9, 1998 (Version 3.1)
7-31
XC3000 Series Field Programmable Gate Arrays
7
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input(s) of the FPGA(s). The serial configuration bitstream
must be available at the DIN input of the lead FPGA a short
set-up time before each rising CCLK edge. The lead device
then presents the preamble data (and all data that over-
flows the lead device) on its DOUT pin. There is an internal
delay of 0.5 CCLK periods, which means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy-chain accepts data on the subsequent rising
CCLK edge.
D/P
RESET
X5993
FPGA
General-
Purpose
User I/O
Pins
+5 V
M0
M1
PWRDWN
CCLK
DIN
STRB
D0
D1
D2
D3
D4
D5
D6
D7
RESET
I/O
Port
Micro
Computer
DOUT
HDC
LDC
M2
...
Other
I/O Pins
INIT
+5 V
5 k
If Readback is
Activated, a
5-k
Resistor is
Required in
Series with M1
*
Optional
Daisy-Chained
LCAs with
Different
Configurations
*
Figure 29: Slave Serial Mode Circuit Diagram
Product Obsolete or Under Obsolescence
相關(guān)PDF資料
PDF描述
ABC65DRES-S734 CONN EDGECARD 130PS .100 EYELET
A14V40A-PQG160C IC FPGA 4K GATES 3.3V 160-PQFP
EMC18DTEF CONN EDGECARD 36POS .100 EYELET
A1425A-1PQ160I IC FPGA 2500 GATES 160-PQFP
A1440A-PQG160I IC FPGA 4K GATES 160-PQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3042A-7PQ100C0167 制造商:Xilinx 功能描述:
XC3042A-7PQ100C0262 制造商:Xilinx 功能描述:
XC3042A-7PQ100C0341 制造商:Xilinx 功能描述:
XC3042A-7PQ100I 制造商: 功能描述: 制造商:undefined 功能描述:
XC3042A-7PQG100I 制造商:Xilinx 功能描述: