參數(shù)資料
型號(hào)： XC2S100E-6TQG144C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 39/108頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 1.8V 600 CLB'S 144-TQFP
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝： 60
系列： Spartan®-IIE
LAB/CLB數(shù)： 600
邏輯元件/單元數(shù)： 2700
RAM 位總計(jì)： 40960
輸入/輸出數(shù)： 102
門數(shù)： 100000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
其它名稱： 122-1462
36
DS077-3 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin)
Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin)
Symbol
Description
Speed Grade
Units
-7
-6
Min
TPSDLL / TPHDLL
Input setup and hold time relative to global clock input signal
for LVTTL standard, no delay, IFF,(1) with DLL
1.6 / 0
1.7 / 0
ns
Notes:
1.
IFF = Input Flip-Flop or Latch
2.
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3.
DLL output jitter is already included in the timing calculation.
4.
For data input with different standards, adjust the setup time delay by the values shown in IOB Input Delay Adjustments for Different
Standards, page 38. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
5.
A zero hold time listing indicates no hold time or a negative hold time.
Symbol
Description
Device
Speed Grade
Units
-7
-6
Min
TPSFD / TPHFD
Input setup and hold time relative
to global clock input signal for
LVTTL standard, with delay, IFF,(1)
without DLL
XC2S50E
1.8 / 0
ns
XC2S100E
1.8 / 0
ns
XC2S150E
1.9 / 0
ns
XC2S200E
1.9 / 0
ns
XC2S300E
2.0 / 0
ns
XC2S400E
2.0 / 0
ns
XC2S600E
2.1 / 0
ns
Notes:
1.
IFF = Input Flip-Flop or Latch
2.
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3.
For data input with different standards, adjust the setup time delay by the values shown in IOB Input Delay Adjustments for Different
Standards, page 38. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
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參數(shù)描述
XC2S100E-6TQG144I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
XC2S100E7FG456C 制造商:Xilinx 功能描述:
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XC2S100E-7FG456I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family
XC2S100E-7FG676C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
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