參數(shù)資料
型號： XC2S100E-6TQG144C
廠商： Xilinx Inc
文件頁數(shù)： 2/108頁
文件大小： 0K
描述： IC FPGA 1.8V 600 CLB'S 144-TQFP
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標準包裝： 60
系列： Spartan®-IIE
LAB/CLB數(shù)： 600
邏輯元件/單元數(shù)： 2700
RAM 位總計： 40960
輸入/輸出數(shù)： 102
門數(shù)： 100000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
其它名稱： 122-1462
10
DS077-2 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Input/Output Block
The Spartan-IIE FPGA IOB, as seen in Figure 4, features
inputs and outputs that support a wide variety of I/O signal-
ing standards. These high-speed inputs and outputs are
capable of supporting various state of the art memory and
bus interfaces. The default standard is LVTTL. Table 3 lists
several of the standards which are supported along with the
required reference (VREF), output (VCCO) and board termi-
nation (VTT) voltages needed to meet the standard. For
more details on the I/O standards and termination applica-
tion examples, see XAPP179, "Using SelectIO Interfaces in
Spartan-II and Spartan-IIE FPGAs."
The three IOB registers function either as edge-triggered
D-type flip-flops or as level-sensitive latches. Each IOB has
a clock signal (CLK) shared by the three registers and inde-
pendent Clock Enable (CE) signals for each register.
In addition to the CLK and CE control signals, the three reg-
isters share a Set/Reset (SR). For each register, this signal
can be independently configured as a synchronous Set, a
synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
A feature not shown in the block diagram, but controlled by
the software, is polarity control. The input and output buffers
and all of the IOB control signals have independent polarity
controls.
Figure 4: Spartan-IIE Input/Output Block (IOB)
Package Pin
Package
Pin
Package Pin
D
CK
EC
SR
Q
D
CK
EC
SR
Q
D
CK
EC
SR
Q
Programmable
Bias and
ESD Network
VCCO
I/O
I/O, VREF
Internal
Reference
To Next I/O
To Other
External VREF Inputs
of Bank
Notes:
1. For some I/O standards.
Programmable
Input Buffer
Programmable
Output Buffer
Programmable
Delay
VCC
VCC(1)
OE
SR
O
OCE
I
ICE
IQ
CLK
TCE
T
DS077-2_01_051501
TFF
OFF
IFF
Table 3: Standards Supported by I/O (Typical Values)
I/O Standard
Input
Reference
Voltage
(VREF)
Input
Voltage
(VCCO)
Output
Source
Voltage
(VCCO)
Board
Termination
Voltage
(VTT)
LVTTL (2-24 mA)
N/A
3.3
N/A
LVCMOS2
N/A
2.5
N/A
LVCMOS18
N/A
1.8
N/A
PCI (3V,
33 MHz/66 MHz)
N/A
3.3
N/A
GTL
0.8
N/A
1.2
GTL+
1.0
N/A
1.5
HSTL Class I
0.75
N/A
1.5
0.75
HSTL Class III
0.9
N/A
1.5
HSTL Class IV
0.9
N/A
1.5
SSTL3 Class I
and II
1.5
N/A
3.3
1.5
SSTL2 Class I
and II
1.25
N/A
2.5
1.25
CTT
1.5
N/A
3.3
1.5
AGP
1.32
N/A
3.3
N/A
LVDS, Bus LVDS
N/A
2.5
N/A
LVPECL
N/A
3.3
N/A
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