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參數(shù)資料
| 型號(hào)： | XC167CS-32F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontroller with C166SV2 Core |
| 中文描述： | 16位單片機(jī)與C166SV2核心 |
| 文件頁(yè)數(shù)： | 83/90頁(yè) |
| 文件大小： | 888K |
| 代理商： | XC167CS-32F |
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XC167-32
Derivatives
Electrical Parameters
Data Sheet
81
V1.0, 2005-06
Bus Cycle Control via READY Input
The duration of an external bus cycle can be controlled by the external circuitry via the
READY input signal. The polarity of this input signal can be selected.
Synchronous
READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
Asynchronous
READY puts no timing constraints on the input signal but incurs one
waitstate minimum due to the additional synchronization stage. The minimum duration
of an asynchronous READY signal to be safely synchronized must be one CLKOUT
period plus the input setup time.
An active READY signal can be deactivated in response to the trailing (rising) edge of
the corresponding command (RD or WR).
If the next following bus cycle is READY-controlled, an active READY signal must be
disabled before the first valid sample point for the next bus cycle. This sample point
depends on the programmed phases of the next following cycle.
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