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參數(shù)資料
| 型號(hào)： | XC167CS-32F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontroller with C166SV2 Core |
| 中文描述： | 16位單片機(jī)與C166SV2核心 |
| 文件頁數(shù)： | 49/90頁 |
| 文件大?。?/td> | 888K |
| 代理商： | XC167CS-32F |
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XC167-32
Derivatives
Functional Description
Data Sheet
47
V1.0, 2005-06
3.12
High Speed Synchronous Serial Channels (SSC0/SSC1)
The High Speed Synchronous Serial Channels SSC0/SSC1 support full-duplex and half-
duplex synchronous communication. It may be configured so it interfaces with serially
linked peripheral components, full SPI functionality is supported.
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling three separate interrupt
vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit error and receive error supervise the correct
handling of the data buffer. Phase error and baudrate error detect incorrect serial data.
Summary of Features
Master or Slave mode operation
Full-duplex or Half-duplex transfers
Baudrate generation from 20 Mbit/s to 305.18 bit/s (@ 40 MHz)
Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB-first or MSB-first
– Programmable clock polarity: idle low or idle high
– Programmable clock/data phase: data shift with leading or trailing clock edge
Loop back option available for testing purposes
Interrupt generation on transmitter buffer empty condition, receive buffer full
condition, error condition (receive, phase, baudrate, transmit error)
Three pin interface with flexible SSC pin configuration
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