參數(shù)資料
型號(hào)： XC161CJ-16F
廠商： INFINEON TECHNOLOGIES AG
英文描述： 16-Bit Single-Chip Microcontroller with C166SV2 Core
中文描述： 16位單片機(jī)與C166SV2核心
文件頁(yè)數(shù)： 72/87頁(yè)
文件大?。?/td> 807K
代理商： XC161CJ-16F
XC161-16
Derivatives
Electrical Parameters
Data Sheet
70
V2.3, 2006-03
4.4.2
On-chip Flash Operation
The XC161’s Flash module delivers data within a fixed access time (see
Table 17
).
Accesses to the Flash module are controlled by the PMI and take 1+WS clock cycles,
where WS is the number of Flash access waitstates selected via bitfield WSFLASH in
register IMBCTRL. The resulting duration of the access phase must cover the access
time
t
ACC
of the Flash array. Therefore, the required Flash waitstates depend on the
available speed grade as well as on the actual system frequency.
Note: The Flash access waitstates only affect non-sequential accesses. Due to
prefetching mechanisms, the performance for sequential accesses (depending on
the software structure) is only partially influenced by waitstates.
In typical applications, eliminating one waitstate increases the average
performance by 5%
…
15%.
Example: For an operating frequency of 40 MHz (clock cycle = 25 ns), devices can be
operated with 1 waitstate: ((1+1)
×
25 ns)
≥
50 ns.
Table 18
indicates the interrelation of waitstates and system frequency.
Note: The maximum achievable system frequency is limited by the properties of the
respective derivative, i.e. 40 MHz (or 20 MHz for xxx-16F20F devices).
Table 17
Flash Characteristics
(Operating Conditions apply)
Parameter
Symbol
Limit Values
Typ.
–
2
1)
200
1)
Unit
Min.
–
–
–
Max.
50
5
500
Flash module access time
Programming time per 128-byte block
Erase time per sector
t
ACC
t
PR
t
ER
CC
CC
CC
ns
ms
ms
1) Programming and erase time depends on the system frequency. Typical values are valid for 40 MHz.
Table 18
Flash Access Waitstates
Required Waitstates
0 WS (WSFLASH = 00
B
)
1 WS (WSFLASH = 01
B
)
Frequency Range
f
CPU
≤
20 MHz
f
CPU
≤
40 MHz
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