參數(shù)資料
型號： XC161CJ-16F
廠商： INFINEON TECHNOLOGIES AG
英文描述： 16-Bit Single-Chip Microcontroller with C166SV2 Core
中文描述： 16位單片機(jī)與C166SV2核心
文件頁數(shù)： 15/87頁
文件大?。?/td> 807K
代理商： XC161CJ-16F
XC161-16
Derivatives
General Device Information
Data Sheet
13
V2.3, 2006-03
P3
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.15
59
60
61
62
63
64
65
66
67
68
69
70
75
76
77
IO
I
O
I
O
I/O
I
I
O
I
I
I
I
I/O
I/O
O
I
I/O
I
O
O
I
I/O
I
O
O
I
I
O
I
Port 3 is a 15-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 3 is selectable (standard
or special).
The following Port 3 pins also serve for alternate functions:
T0IN
CAPCOM1 Timer T0 Count Input,
TxD1
ASC1 Clock/Data Output (Async./Sync),
EX1IN
Fast External Interrupt 1 Input (alternate pin B)
T6OUT
GPT2 Timer T6 Toggle Latch Output,
RxD1
ASC1 Data Input (Async.) or Inp./Outp. (Sync.),
EX1IN
Fast External Interrupt 1 Input (alternate pin A)
CAPIN
GPT2 Register CAPREL Capture Input
T3OUT
GPT1 Timer T3 Toggle Latch Output
T3EUD
GPT1 Timer T3 External Up/Down Control Input
T4IN
GPT1 Timer T4 Count/Gate/Reload/Capture Inp
T3IN
GPT1 Timer T3 Count/Gate Input
T2IN
GPT1 Timer T2 Count/Gate/Reload/Capture Inp
MRST0
SSC0 Master-Receive/Slave-Transmit In/Out.
MTSR0
SSC0 Master-Transmit/Slave-Receive Out/In.
TxD0
ASC0 Clock/Data Output (Async./Sync.),
EX2IN
Fast External Interrupt 2 Input (alternate pin B)
RxD0
ASC0 Data Input (Async.) or Inp./Outp. (Sync.),
EX2IN
Fast External Interrupt 2 Input (alternate pin A)
BHE
External Memory High Byte Enable Signal,
WRH
External Memory High Byte Write Strobe,
EX3IN
Fast External Interrupt 3 Input (alternate pin B)
SCLK0
SSC0 Master Clock Output/Slave Clock Input.,
EX3IN
Fast External Interrupt 3 Input (alternate pin A)
CLKOUT
Master Clock Output,
FOUT
Programmable Frequency Output
Debug System: JTAG Clock Input
Debug System: JTAG Data In
Debug System: JTAG Data Out
Debug System: JTAG Test Mode Selection
TCK
TDI
TDO
TMS
71
72
73
74
Table 2
Pin Definitions and Functions
(cont’d)
Sym-
bol
Pin
Num.
Input
Outp.
Function
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