參數(shù)資料
型號: XC161CJ-16F
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller with C166SV2 Core
中文描述: 16位單片機與C166SV2核心
文件頁數(shù): 11/87頁
文件大?。?/td> 807K
代理商: XC161CJ-16F
XC161-16
Derivatives
General Device Information
Data Sheet
9
V2.3, 2006-03
Table 2
Pin Definitions and Functions
Sym-
bol
P20.12
NMI
Pin
Num.
3
4
Input
Outp.
IO
I
Function
For details, please refer to the description of
P20
.
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the XC161 into power down
mode. If NMI is high, when PWRDN is executed, the part will
continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
Port 6 is an 8-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 6 is selectable (standard
or special).
The Port 6 pins also serve for alternate functions:
CS0
Chip Select 0 Output,
CC0IO
CAPCOM1: CC0 Capture Inp./Compare Output
CS1
Chip Select 1 Output,
CC1IO
CAPCOM1: CC1 Capture Inp./Compare Output
CS2
Chip Select 2 Output,
CC2IO
CAPCOM1: CC2 Capture Inp./Compare Output
CS3
Chip Select 3 Output,
CC3IO
CAPCOM1: CC3 Capture Inp./Compare Output
CS4
Chip Select 4 Output,
CC4IO
CAPCOM1: CC4 Capture Inp./Compare Output
HOLD
External Master Hold Request Input,
CC5IO
CAPCOM1: CC5 Capture Inp./Compare Output
HLDA
Hold Acknowledge Output (master mode) or
Input (slave mode),
CC6IO
CAPCOM1: CC6 Capture Inp./Compare Output
BREQ
Bus Request Output,
CC7IO
CAPCOM1: CC7 Capture Inp./Compare Output
P6
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
7
8
9
10
11
12
13
14
IO
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
I
I/O
O/I
I/O
O
I/O
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