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參數(shù)資料
| 型號： | X80010 |
| 廠商： | Intersil Corporation |
| 英文描述： | Penta-Power Sequence Controller with Hot swap and System Management |
| 中文描述： | 季戊四醇功率序列熱插拔控制器和系統(tǒng)管理 |
| 文件頁數(shù)： | 19/25頁 |
| 文件大小： | 548K |
| 代理商： | X80010 |
19
FN8149.0
January 13, 2005
Quad Voltage Monitoring
X80010 monitors 4 voltage enable inputs. When the ENi
(i=1-4) input is detected to be below the input threshold, the
output ViGOOD (i = 1 to 4) goes active LOW. The ViGOOD
signal is asserted after a delay of 100ms. The ViGOOD
signal remains active until ENi rises above threshold.
Once the PWRGD signal is asserted, the power sequencing
of the DC/DC modules can commence. RESET goes active
100ms after all ViGOOD (i=1 to 4) outputs are asserted (See
Figure 39).
As shown in Figure 40, this circuit block contains four
separate voltage enable pins, a time delay circuit, and an
output driver.
Control
Registers
RESET Logic
t
SPOR
Delay
SPOR
MRC
V
DD
Drain Sense
& Power
Good Logic
Enable
Logic
RESET
PWRGD
ViGOOD
i = 1 to 4
μ
P
V
EE
FIGURE 39. POWER ON/SYSTEM RESET AND DELAY
EN1
EN2
EN3
EN4
V4GOOD
V3GOOD
V2GOOD
V1GOOD
V
EE
Divider
Reset
4
OSC
0.1s
0.5s
1s
5s
Select
4
delay1
delay2
delay3
delay4
Delay circuit
repeated 4 times
V
RGO
Control Register
FIGURE 40. VOLTAGE MONITORS AND VGOOD OUTPUTS
X80010, X80011, X80012, X80013
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