參數(shù)資料
型號： X80000Q32I
廠商： INTERSIL CORP
元件分類： 電源管理
英文描述： Smart Power Plug Penta-Power Sequence Controller with Hot Swap
中文描述： 5-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32
封裝： 7 X 7 MM, 0.65 MM PITCH, QFN-32
文件頁數(shù)： 35/37頁
文件大小： 695K
代理商： X80000Q32I
35
FN8148.0
March 18, 2005
Serial Read Operations
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the Slave
Address Byte is set to one. There are three basic read
operations: Current Address Reads, Random Reads, and
Sequential Reads.
Random Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master issues
the start condition and the Slave Address Byte, receives an
acknowledge, then issues the Word Address Bytes. After
acknowledging receipts of the Word Address Bytes, the
master immediately issues another start condition and the
Slave Address Byte with the R/W bit set to one. This is
followed by an acknowledge from the device and then by the
eight bit word. The master terminates the read operation by
not responding with an acknowledge and then issuing a stop
condition. See Figure 42 for the address, acknowledge, and
data transfer sequence.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n+1. On
power up, the address of the address counter is undefined,
requiring a read or write operation for initialization.
Upon receipt of the Slave Address Byte with the R/W bit set
to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond with
an acknowledge during the ninth clock and then issues a
stop condition. See Figure 43 or the address, acknowledge,
and data transfer sequence.
Operational Notes
The device powers-up in the following state:
The device is in the low power standby state.
The WEL bit is set to ‘0’. In this state, it is not possible to
write to the device.
SDA pin is the input mode.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
The WEL bit must be set to allow write operations.
The proper clock count and bit sequence is required prior
to the stop bit in order to start a nonvolatile write cycle.
ACK
Returned
Issue Slave Address
Byte (Read or Write)
Byte Load Completed by
Issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
High Voltage Cycle
Complete. Continue
Command Sequence
Issue STOP
NO
Continue Normal Read
or Write Command
Sequence
PROCEED
YES
FIGURE 44. ACKNOWLEDGE POLLING SEQUENCE
X80000, X80001
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